Getting Started with AMD

标签：Engine FPGA Getting Started AMD AI applications Vitis

FPGA and definitions

BEL - Basic Element of Logic

BEL is the lowest basic element (the smallest and indivisible component in FPGA), and it can also be called aotomic unit.

Logic BEL: a configurable logic-based site
Routing BEL: programmable routing muxes

Site - Collection of BELs

A group of related elements and their connectivity

BELs (Logic BELs and/or Routing BELs)
Site Pins (External input and output pins to the site)
Site wires (connecting elements to each other and site pins)

Tile - Collection of Sites

At an abstract level, Xilinx device are created by assembling a grid of tiles. Similar to sites, each tile is an instance of a type.

Tiles are the building blocks used when constructing and FPGA device. Tiles are designed to about one another when laid down to construct an FPGA device.

FSR - Fabric Sub Region or Clock Region

SLR - Super Logic Region

Device - Collection of SLRs

Vitis - Make FPGA Programming Easy

The Vitis™ Unified Software Platform is a cutting-edge application that streamlines the FPGA programming process for software engineers, data scientists, and AI developers. It includes an expansive open-source library optimized for AMD FPGA and ACAP hardware platforms, and a core development kit that allows you to seamlessly build accelerated applications without extensive hardware experience.

Vitis™ also includes the Vitis Model Composer, which offers a toolbox within MATLAB® and Simulink®. It streamlines the process of designing and testing new applications.

What is AIE ? - AMD AI Engine Technology

AI Engine(AIE) and FPGA are both part of AMD XDNA.
AIE will come to Ryzen and Epyc and make them vastly more capable for AI applications.

Increased Compute Density and Silicon Efficiency for Heterogeneous Acceleration.

Responding to non-linear increase in demand by next-generation applications, AMD had developed a new innovative processing technology, the AI Engine, as part of the Versal Adaptive Compute Acceleration Platforn(ACAP) architecture.

AI Engine Architecture

AI Egines are architected as 2D arrays consisting of multiple AI Engine tiles and allow for a very scalable solution across the Versal portfolio.

AI Engine Tile

Heterogeneous Workloads: Signal Processing and Machine Learning Inference Acceleration

heterogeneous-workloads

AI Engine-ML Tile

The AI Engine-ML architecture is optimized for machine learning, enhancing both the compute core and memory architecture.

Part of a Heterogeneous Platform

The AI Engine along with Adaptable Engines (programmable logic) and Scalar Engines (processor subsystem) form a tightly integrated heterogeneous architecture on Versal Adaptive Compute Acceleration Platforms (ACAPs) that can be changed at both the hardware and software levels to dynamically adapt to the needs of a wide range of applications and workloads.

What is CDNA ?

AMD RDNA: optimized for gaming to maximize frames per second
AMD CDNA: optimized for computing to push the limits of flops per second

What is XDNA ?

The foundational architecture IP from Xilinx that consists of key technologies including the FPGA fabric and AI Engine (AIE).

How to understand software stack ?

AMD's and XILINX's software stack will be unified to access AI capability across Zen, RDNA, CDNA and XDNA.

What is Vitis Unified Software Platform ?

Software Development Platform Overview Block Diagram

Vitis AI Development Environment

The Vitis AI development environment is a specialized development environment for accelerating AI inference on AMD embedded platforms, Alveo accelerator cards, or on the FPGA-instances in the cloud.

Vitis Accelerated Libraries

Open-source, performance-optimized libraries that offer out-of-the-box acceleration with minimal to zero-code changes to your existing applications.

VItis Core Development Kit

A complete set of graphical and command-line developer tools that include the Vitis compilers, analyzers, and debuggers to build applications, analyze performance bottlenecks, and debug accelerated algorithms.

Xilinx Runtime library

XRT includes user-space libraries and APIs, kernel drivers, board utilities, and firmware.

Vitis Target Platforms

The Vitis target platform defines base hardware and software architecture and application context for AMD platforms, including external memory interfaces, custom input/output interfaces, and software runtime.

Vitis Model Composer

Vitis Model Composer is an AMD toolbox for the MATLAB and Simulink environment that enables rapid design exploration and verification within the MATLAB and Simulink tool and accelerates the path to production on AMD devices.

What is Vitis AI ?

Optimal Artificial Intelligence Inference from Edge to Cloud

The Vitis™ AI platform is a comprehensive AI inference development solution for AMD devices, boards, and Alveo™ data center acceleration cards. It consists of a rich set of AI models, optimized deep learning processor unit (DPU) cores, tools, libraries, and example designs for AI at the edge and in the data center. It is designed with high efficiency and ease of use in mind, unleashing the full potential of AI acceleration on AMD FPGAs and adaptive SoCs.

AI Model Zoo

AI Optimizer

Model compression technology, which reduces model complexity with minimal accuracy impacrt.

Artificial Intelligence Optimizer Block Diagram

AI Quantizer

providing faster speed and higher computing efficiency - A completed process of custom operator inspection, quantization, calibration, fine-tuning, and converting floating-point models into fixed-point models that requires less memory bandwidth.

Artificial Intelligence Quantizer Block Diagram

AI Compiler

Maps the AI model to a highly efficient instruction set and data flow.

Also performs sophisticated optimizations, and reuses on-chip memory as much as possible.

Artificial Intelligence Compiler Block Diagram

AI Profiler

Allows programmers to perform in-depth analysis of the efficiency and utilization of the AI inference implementation.

AI Library

A set of high-level libraries and APIs built for efficient AI inference with DPU cores.

Built based on the Vitis AI Runtime (VART) with unified APIs and provides easy-to-use interfaces for AI model deployment on AMD platforms.

Artificial Intelligence Library Block Diagram

Whole Graphic Optimizer (WeGO)

Offers a straightforward path from training to inference by leveraging native TensorFlow or PyTorch frameworks to deploy DPU unsupported operators to the CPU—greatly speeding up model deployment and evaluation over cloud DPUs.

Whole Graphic Optimizer (WeGO) Block Diagram