1、riscduino
仓库地址：https://github.com/dineshannayya/riscduino
Riscduino is a Single 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
2、Ibex RISC-V Core
仓库地址：https://github.com/lowRISC/ibex
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
3、NEORV32、NEO430
仓库地址：https://github.com/stnolting/neorv32
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) built around the NEORV32 RISC-V CPU and written in platform-independent VHDL. The processor is intended as auxiliary controller in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus low-power & low-density FPGA. The project is intended to work out of the box and targets FPGA / RISC-V beginners as well as advanced users.
仓库地址：https://github.com/stnolting/neo430
4、MSP430
仓库地址：https://opencores.org/projects/openmsp430
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.
The core comes with some peripherals (16x16 Hardware Multiplier, Watchdog, GPIO, TimerA, generic templates), with a DMA interface, and most notably with a two-wire Serial Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system software debugging.
5、wujian100_open
仓库地址：https://github.com/T-head-Semi/wujian100_open
6、平头哥开源
仓库地址：https://github.com/T-head-Semi
7、PicoRV32
仓库地址：https://github.com/YosysHQ/picorv32
PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.
8、开源核
ZipCPU UART：https://github.com/ZipCPU/wbuart32
Alexforencich IIC：https://github.com/alexforencich/verilog-i2c
C910核附带UART：https://github.com/MeDove/openc910/tree/main/smart_run/logical
9、开源网站
OpenCores：https://opencores.org/projects
Alexforencich：http://alexforencich.com/wiki/en/verilog/start
ZipCpu：http://zipcpu.com/tutorial/
RISC-V：https://github.com/T-head-Semi/openc910
标签：core,优质,github,FPGA,仓库,RISC,开源,https,com From： https://www.cnblogs.com/breakr-yu/p/17132845.html