1.interface作用
(1) 简化port connections,简化RTL coding;
(2) 功能覆盖率的收集;
(3) 协议检查与断言;
2.interface语法
(1) interface就是一组nets或者variables;
(2) interface与类比较相像,interface可以有参数,常量,变量,function以及task;除此之外,interface还可以包含进程,比如initial块或always块;
(3) interface可以在module内部声明与例化,但module既不能在interface内声明,也不能在interface内例化;
(4) interface内的nets或variable默认为ref或inout类型;
2.1 简单的interface (没有端口)
interface identifier;
...
interface items
...
endinterface : identifier
interface simple_bus;
logic req, gnt;
logic [7:0] addr,data;
logic [1:0] mode;
logic start,rdy;
endinterface: simple_bus
module memMode(simple_bus a, input logic clk);
logic avail;
always @(posedge clk) a.gnt<=a.req & avail;
endmodule
module cpuMod(simple_bus b, input logic clk);
...
endmodule
module top;
logic clk=0;
simple_bus sb_intf();
memMod mem(sb_intf,clk);
cpuMode cpu(.b(sb_intf),.clk(clk));
endmodule
2.2 有端口的interface
(1) 简单interface的缺点在于interface内声明的nets以及variables只能连接向具有相同名字nets以及variables的端口;
interface i1(input a, output b, inout c);
wire d;
endinterface
3.interface modports
(1) modports可以限制interface access;
(2) 声明modports用到的名字都需要在相同的interface里面声明过;
interface i2;
wire a, b, c, d;
modport master (input a, b, output c, d);
modport slave (output a, b, input c, d);
endinterface
module m (i2.master i);
...
endmodule
module s (i2.slave i);
...
endmodule
module top;
i2 i();
m u1(.i(i));
s u2(.i(i));
endmodule
另外一种用法:
module m (i2 i);
...
endmodule
module s(i2 i);
...
endmodule
module top;
i2 i();
m u1(.i(i.master));
s u2(.i(i.slave));
endmodule
modport示例:
interface simple_bus(input logic clk);
logic req, gnt;
logic [7:0] addr,data;
logic [1:0] mode;
logic start, rdy;
modport slave(input req, addr, mode, start, clk,
output gnt, rdy,
ref data);
modport master(input gnt, rdy, clk,
output req, addr, mode, start,
ref data);
endinterface: simple_bus
module memMod(simple_bus.slave a);
logic avail;
always @(posedge a.clk)
a.gnt<=a.req & avail;
endmodule
module cpuMod(simple_bus.master b);
...
endmodule
module top;
logic clk=0;
simple_bus sb_intf(clk);
initial repeat(10) #10 clk++;
memMod mem(.a(sb_intf));
cpuMod cpu(.b(sb_intf));
endmodule
3.1 clocking blocks & modports
interface A_Bus(input logic clk);
wire req, gnt;
wire [7:0] addr,data;
clocking sb @(posedge clk);
input gnt;
output req, addr;
inout data;
property p1;
req ##[1:3] gnt;
endproperty
endclocking
//Device under test modport
modport DUT (input clk, req, addr, output gnt, inout data);
//synchronous testbench modport
modport STB (clocking sb);
//asynchronous testbench modport
modport TB (input gnt, output req, addr, inout data);
endinterface
module dev1(A_Bus.DUT b);
...
endmodule
module dev2(A_Bus.DUT b);
...
endmodule
program T(A_Bus.STB b1, A_Bus.STB b2);
assert property(b1.sb.p1);
initial begin
b1.sb.req<=1;
wait(b1.sb.gnt==1);
...
b1.sb.req<=0;
b2.sb.req<=1;
wait(b2.sb.gnt==1);
...
b2.sb.req<=0;
end
endprogram
module top;
logic clk;
A_Bus b1(clk);
A_Bus b2(clk);
dev1 d1(b1);
dev2 d2(b2);
T tb(b1,b2);
endmodule
4.interface methods