基于 VScode 搭建 Verilog 自动格式化

插件

• Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
• SystemVerilog and Verilog Formatter

工具

https://github.com/google/verible

https://github.com/universal-ctags/ctags-win32/releases

配置

  "systemverilogFormatter.veribleBuild": "win64",
  "systemverilogFormatter.commandLineArguments": "--column_limit=300 --indentation_spaces=2 --assignment_statement_alignment=align --named_port_alignment=align  --port_declarations_alignment=align --module_net_variable_alignment=align",
  "verilog.ctags.path": "C:\\Users\\Administrator\\Documents\\Tools\\ctags\\ctags.exe"