目录
概述
本文主要介绍基于STM32芯片实现DRV8353RS的驱动程序，文中介绍DRV8353RS的SPI接口的时序，还介绍了主要的驱动程序接口，并验证了该程序的功能。
1. 硬件接口定义
1.1 DRV8353RS的SPI控制模块
1） DRV8353RS与MCU之间的通信接口
2）使能DRV8353RS控制接口
1.2 时序介绍
在DRV835x SPI设备上，SPI总线用于设置设备配置、运行参数和读取诊断信息。SPI在从属模式下工作并连接到主控制器。SPI输入数据（SDI）字由一个16位字、一个5位命令和11位数据组成。SPI输出数据（SDO）字由11位寄存器数据组成。前5位是无所谓位。
一个有效的帧必须满足以下条件：
•当nSCS引脚：从高到低和从低到高转换时，SCLK引脚应该是低的。
•nSCS引脚： 应在单词之间至少拉高400ns。
•当nSCS引脚： 被拉高时，在SCLK和SDI引脚的任何信号都被忽略，SDO引脚被设置
Hi-Z。数据在SCLK的下降沿上捕获，数据在SCLK的上升沿上传播。最高有效位（MSB）首先被移进移出。
•事务必须经过16个SCLK周期才有效。
•如果发送到SDI引脚的数据字不是16位，则会发生帧错误并忽略该数据字。
•对于写命令，要写入的寄存器中的现有数据在SDO引脚上跟随5位命令数据移出。
•SDO引脚是一个开漏输出，需要一个外部上拉电阻。
1.3 数据格式
SDI输入数据字长16位，由以下格式组成：
•1个读写位， W （B15位）
•4个地址位， A （B14到B11位）
•11位数据位 D （ B11到B0位）
设置写命令的读写位（W0, B15）为0b。设置读命令的读写位（W0, B15）为1b。
设置W0( B15 ) = 0: 写参数模式使能
设置W0( B15 ) = 1: 读参数模式使能
SDO输出数据字长16位，前5位是无关位。响应字是当前正在访问的寄存器中的数据。
1）SDI Input Data Word Format：
2）SDO Output Data Word Format：
3）SPI Slave Timing Diagram
4）Register Map
2 驱动代码实现
2.1 STM32Cube配置接口
配置SPI2为MCU和DRV8353RS的通信接口，PB10用于使能芯片
2.2 驱动程序实现
2.2.1 接口函数实现
1） 定义输入参数数据结构
2） 写参数函数
3）读参数函数
2.2.2 default参数配置
定义默认配置参数数据结构
2.2.3 初始化函数
1）读取芯片内部参数
2）修改和配置参数
2.2.4 读取状态函数
1）状态寄存器数据结构
2）函数体
3 驱动程序测试
3.1 参数初始化
3.2 测试函数实现
如下函数实现主要功能如下：
1）使能和复位芯片
2） 读取和配置参数
void DRV835X_updateCfgPara( void )
{
uint16_t data;
stru_DRV8353Obj.drvCtrl_obj.data = read_reg( DCR );
stru_DRV8353Obj.drvCsa_obj.data = read_reg( CSACR );
stru_DRV8353Obj.drvCfg_obj.data = read_reg( DFGCR );
stru_DRV8353Obj.drvGateHS_obj.data = read_reg( HSR );
stru_DRV8353Obj.drvGateLS_obj.data = read_reg( LSR );
stru_DRV8353Obj.drvOcp_obj.data = read_reg( OCPCR );
stru_DRV8353Obj.faultStatusReg1_obj.data = read_reg( FSR1 );
stru_DRV8353Obj.faultStatusReg2_obj.data = read_reg( FSR2 );
// Driver Control Register (address = 0x02h)
stru_DRV8353Obj.drvCtrl_obj.ctrlRegObj.PWM_MODE = stru_config.PWM_MODE;
data = stru_DRV8353Obj.drvCtrl_obj.data;
write_reg( DCR, data);
//Gate Drive HS Register (address = 0x03h)
stru_DRV8353Obj.drvGateHS_obj.gateHSRegObj.IDRIVEP_HS = stru_config.IDRIVEP_HS;
stru_DRV8353Obj.drvGateHS_obj.gateHSRegObj.IDRIVEN_HS = stru_config.IDRIVEN_HS;
stru_DRV8353Obj.drvGateHS_obj.gateHSRegObj.LOCK = stru_config.LOCK;
data = stru_DRV8353Obj.drvGateHS_obj.data;
write_reg( HSR, data);
// Gate Drive LS Register (address = 0x04h)
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.IDRIVEN_LS = stru_config.IDRIVEN_LS;
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.IDRIVEP_LS = stru_config.IDRIVEP_LS;
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.TDRIVE = stru_config.TDRIVE;
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.CBC = stru_config.CBC;
data = stru_DRV8353Obj.drvGateLS_obj.data;
write_reg( LSR, data);
// OCP Control Register (address = 0x05h)
stru_DRV8353Obj.drvOcp_obj.ocpObj.VDS_LVL = stru_config.VDS_LVL;
stru_DRV8353Obj.drvOcp_obj.ocpObj.OCP_DEG = stru_config.OCP_DEG;
stru_DRV8353Obj.drvOcp_obj.ocpObj.OCP_MODE = stru_config.OCP_MODE;
stru_DRV8353Obj.drvOcp_obj.ocpObj.DEAD_TIME = stru_config.DEAD_TIME;
data = stru_DRV8353Obj.drvOcp_obj.data;
write_reg( OCPCR, data);
// CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
stru_DRV8353Obj.drvCsa_obj.csaObj.SEN_LVL = stru_config.SEN_LVL;
stru_DRV8353Obj.drvCsa_obj.csaObj.CSA_GAIN = stru_config.CSA_GAIN;
stru_DRV8353Obj.drvCsa_obj.csaObj.VREF_DIV = stru_config.VREF_DIV;
data = stru_DRV8353Obj.drvCtrl_obj.data;
write_reg( CSACR, data);
}
void DRV835X_Init( void )
{
DRV835X_ENABLE_LOW;
HAL_Delay(100);
DRV835X_ENABLE_HIGH;
HAL_Delay(100);
// SET PWML to low
DRV835X_PWML_LOW;
HAL_Delay(200);
DRV835X_updateCfgPara();
}3.3 测试
1) 读取参数
参数数据如下：
2）跟新数据后参数如下：
更新后的数据
4 源代码文件
1）drv_DRV835X.c文件
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : drv_DRV835X.c
* Description : DRV835X driver
******************************************************************************
* @attention
*
* COPYRIGHT: Copyright (c) 2025
* CREATED BY: ming fei.tang
* DATE: January 04th, 2025
******************************************************************************
*/
/* USER CODE END Header */
#include "drv_DRV835X.h"
/* Private macro -------------------------------------------------------------*/
extern SPI_HandleTypeDef hspi2;
/* Private define ------------------------------------------------------------*/
#define TIME_OUT 100
#define DEFAULT_GAIN 10
#define DRV835X_SPI_Handle hspi2
// DRV8353 SPI CS PIN
#define DRV835X_CS_EN HAL_GPIO_WritePin(SPI2_NSS_GPIO_Port,SPI2_NSS_Pin,GPIO_PIN_RESET)
#define DRV835X_CS_DIS HAL_GPIO_WritePin(SPI2_NSS_GPIO_Port,SPI2_NSS_Pin,GPIO_PIN_SET)
// DRV8353 ENABLE PIN
/*
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode.
An 8 to 40-µs low pulse can be used to reset fault conditions.
*/
#define DRV835X_ENABLE_LOW HAL_GPIO_WritePin(ENABLE_GPIO_Port,ENABLE_Pin,GPIO_PIN_RESET)
#define DRV835X_ENABLE_HIGH HAL_GPIO_WritePin(ENABLE_GPIO_Port,ENABLE_Pin,GPIO_PIN_SET)
// DRV8353 PWML PIN: INLA INLB INLC
/*
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
*/
#define DRV835X_PWML_LOW HAL_GPIO_WritePin(PWML_GPIO_Port,PWML_Pin,GPIO_PIN_RESET)
#define DRV835X_PWML_HIGH HAL_GPIO_WritePin(PWML_GPIO_Port,PWML_Pin,GPIO_PIN_SET)
/* Private variables ---------------------------------------------------------*/
Stru_DRV835X_Status stru_DRV835X_Status;
Stru_DRV835X stru_DRV8353Obj;
StruDRV835XCfgPara stru_config =
{
// Driver Control Register (address = 0x02h)
.PWM_MODE = PWM_MODE_3X,
// CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
.SEN_LVL = SEN_LVL_0_25, // 00b = Sense OCP 0.25 V
.CSA_GAIN = CSA_GAIN_10, // 01b = 10-V/V shunt amplifier gain
.VREF_DIV = VREF_DIV_2, // 1b = Sense amplifier reference voltage is VREF divided by 2
// OCP Control Register (address = 0x05h)
.VDS_LVL = VDS_LVL_0_94,
.OCP_DEG = OCP_DEG_6US,
.OCP_MODE = OCP_REPORT,
.DEAD_TIME = DEADTIME_400NS,
//Gate Drive HS Register (address = 0x03h)
.IDRIVEP_HS = IDRIVEP_HS_1000MA,
.IDRIVEN_HS = IDRIVEN_HS_2000MA,
.LOCK = LOCK_OFF,
// Gate Drive LS Register (address = 0x04h)
.IDRIVEN_LS = IDRIVEN_LS_2000MA,
.IDRIVEP_LS = IDRIVEP_LS_1000MA,
.TDRIVE = TDRIVE_4000NS,
.CBC = PWM_GIVER_ENABLE, // 1b = For VDS_OCP and SEN_OCP, the fault is cleared when
// a new PWM input is given or after tRETRY
};
/* Private function prototypes -----------------------------------------------*/
static uint16_t read_reg(uint16_t address);
static uint16_t write_reg(uint16_t address, uint16_t data);
void DRV835X_updateCfgPara( void )
{
uint16_t data;
stru_DRV8353Obj.drvCtrl_obj.data = read_reg( DCR );
stru_DRV8353Obj.drvCsa_obj.data = read_reg( CSACR );
stru_DRV8353Obj.drvCfg_obj.data = read_reg( DFGCR );
stru_DRV8353Obj.drvGateHS_obj.data = read_reg( HSR );
stru_DRV8353Obj.drvGateLS_obj.data = read_reg( LSR );
stru_DRV8353Obj.drvOcp_obj.data = read_reg( OCPCR );
stru_DRV8353Obj.faultStatusReg1_obj.data = read_reg( FSR1 );
stru_DRV8353Obj.faultStatusReg2_obj.data = read_reg( FSR2 );
// Driver Control Register (address = 0x02h)
stru_DRV8353Obj.drvCtrl_obj.ctrlRegObj.PWM_MODE = stru_config.PWM_MODE;
data = stru_DRV8353Obj.drvCtrl_obj.data;
write_reg( DCR, data);
//Gate Drive HS Register (address = 0x03h)
stru_DRV8353Obj.drvGateHS_obj.gateHSRegObj.IDRIVEP_HS = stru_config.IDRIVEP_HS;
stru_DRV8353Obj.drvGateHS_obj.gateHSRegObj.IDRIVEN_HS = stru_config.IDRIVEN_HS;
stru_DRV8353Obj.drvGateHS_obj.gateHSRegObj.LOCK = stru_config.LOCK;
data = stru_DRV8353Obj.drvGateHS_obj.data;
write_reg( HSR, data);
// Gate Drive LS Register (address = 0x04h)
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.IDRIVEN_LS = stru_config.IDRIVEN_LS;
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.IDRIVEP_LS = stru_config.IDRIVEP_LS;
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.TDRIVE = stru_config.TDRIVE;
stru_DRV8353Obj.drvGateLS_obj.gateLSRegObj.CBC = stru_config.CBC;
data = stru_DRV8353Obj.drvGateLS_obj.data;
write_reg( LSR, data);
// OCP Control Register (address = 0x05h)
stru_DRV8353Obj.drvOcp_obj.ocpObj.VDS_LVL = stru_config.VDS_LVL;
stru_DRV8353Obj.drvOcp_obj.ocpObj.OCP_DEG = stru_config.OCP_DEG;
stru_DRV8353Obj.drvOcp_obj.ocpObj.OCP_MODE = stru_config.OCP_MODE;
stru_DRV8353Obj.drvOcp_obj.ocpObj.DEAD_TIME = stru_config.DEAD_TIME;
data = stru_DRV8353Obj.drvOcp_obj.data;
write_reg( OCPCR, data);
// CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
stru_DRV8353Obj.drvCsa_obj.csaObj.SEN_LVL = stru_config.SEN_LVL;
stru_DRV8353Obj.drvCsa_obj.csaObj.CSA_GAIN = stru_config.CSA_GAIN;
stru_DRV8353Obj.drvCsa_obj.csaObj.VREF_DIV = stru_config.VREF_DIV;
data = stru_DRV8353Obj.drvCtrl_obj.data;
write_reg( CSACR, data);
}
void DRV835X_Init( void )
{
DRV835X_ENABLE_LOW;
HAL_Delay(100);
DRV835X_ENABLE_HIGH;
HAL_Delay(100);
// SET PWML to low
DRV835X_PWML_LOW;
HAL_Delay(200);
DRV835X_updateCfgPara();
}
void DRV835X_read_FaultStatusReg1(void)
{
stru_DRV8353Obj.faultStatusReg1_obj.data = read_reg( FSR1 );
}
void DRV835X_read_FaultStatusReg2(void)
{
stru_DRV8353Obj.faultStatusReg2_obj.data = read_reg( FSR2 );
}
static uint16_t read_reg(uint16_t address)
{
uint16_t data;
Input_WrReg stru_Input_WrRegObj;
stru_Input_WrRegObj.inputRegObj.WR = R_MODE;
stru_Input_WrRegObj.inputRegObj.ADDRESS = address;
data = stru_Input_WrRegObj.data;
DRV835X_CS_EN;
HAL_SPI_Transmit(&DRV835X_SPI_Handle, (uint8_t *)&data, 1,TIME_OUT);
DRV835X_CS_DIS;
HAL_Delay(1);
DRV835X_CS_EN;
HAL_SPI_Receive(&DRV835X_SPI_Handle, (uint8_t *)&data, 1, TIME_OUT);
DRV835X_CS_DIS;
HAL_Delay(1);
return (data & 0x7FF);
}
static uint16_t write_reg(uint16_t address, uint16_t data)
{
Input_WrReg stru_Input_WrRegObj;
stru_Input_WrRegObj.inputRegObj.WR = W_MODE;
stru_Input_WrRegObj.inputRegObj.ADDRESS = address;
stru_Input_WrRegObj.inputRegObj.DATA = data;
data = stru_Input_WrRegObj.data;
do
{
DRV835X_CS_EN;
HAL_SPI_Transmit(&DRV835X_SPI_Handle, (uint8_t *)&data, 1, TIME_OUT);
DRV835X_CS_DIS;
HAL_Delay(1);
}while (read_reg(address) != (data & 0x7FF));
return 0;
}
/* End of this file */
2） drv_DRV835X.h文件
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : drv_DRV835X.h
* Description : DRV835X driver
******************************************************************************
* @attention
*
* COPYRIGHT: Copyright (c) 2025
* CREATED BY: ming fei.tang
* DATE: January 04th, 2025
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#ifndef DRV835X_H
#define DRV835X_H
#ifdef _cplusplus
extern "C"
{
#endif
#include "main.h"
#include "drv_DRV835X_reg.h"
#define W_MODE 0
#define R_MODE 1
typedef struct
{
uint16_t status_FSR1;
uint16_t status_FSR2;
}Stru_DRV835X_Status;
extern Stru_DRV835X_Status stru_DRV835X_Status;
/*
INPUT data structure
*/
typedef struct
{
uint16_t DATA : 11; // 11 data bits, D (bits B11 through B0)
uint16_t ADDRESS : 4; // 4 address bits, A (bits B14 through B11)
uint16_t WR : 1; // 1 read or write bit, W (bit B15)
}Input_WrReg_bit;
typedef struct
{
union
{
uint16_t data;
Input_WrReg_bit inputRegObj;
};
} Input_WrReg ;
/*
Fault Status Register 1 (address = 0x00h)
*/
typedef struct
{
uint16_t VDS_LC : 1;
uint16_t VDS_HC : 1;
uint16_t VDS_LB : 1;
uint16_t VDS_HB : 1;
uint16_t VDS_LA : 1;
uint16_t VDS_HA : 1;
uint16_t OTSD : 1;
uint16_t UVLO : 1;
uint16_t GDF : 1;
uint16_t VDS_OCP : 1;
uint16_t FAULT : 1;
uint16_t res : 5;
}Fault_StatusReg1_bit;
typedef struct
{
union
{
uint16_t data;
Fault_StatusReg1_bit fault1RegObj;
};
} Fault_StatusReg1 ;
/*
Fault Status Register 2 (address = 0x01h)
*/
typedef struct
{
uint16_t VGS_LC : 1;
uint16_t VGS_HC : 1;
uint16_t VGS_LB : 1;
uint16_t VGS_HB : 1;
uint16_t VDS_LA : 1;
uint16_t VDS_HA : 1;
uint16_t GDUV : 1;
uint16_t OTW : 1;
uint16_t SC_OC : 1;
uint16_t SB_OC : 1;
uint16_t SA_OC : 1;
uint16_t res : 5;
}Fault_StatusReg2_bit;
typedef struct
{
union
{
uint16_t data;
Fault_StatusReg2_bit fault2RegObj;
};
} Fault_StatusReg2;
/*
Driver Control Register (address = 0x02h)
*/
typedef struct
{
uint16_t CLR_FLT : 1;
uint16_t BRAKE : 1;
uint16_t COAST : 1;
uint16_t PWM1_DIR : 1;
uint16_t PWM1_COM : 1;
uint16_t PWM_MODE : 2;
uint16_t OTW_REP : 1;
uint16_t DIS_GDF : 1;
uint16_t DIS_GDUV : 1;
uint16_t OCP_ACT : 1;
uint16_t res : 5;
}Drv_CtrlReg_bit;
typedef struct
{
union
{
uint16_t data;
Drv_CtrlReg_bit ctrlRegObj;
};
} Drv_CtrlReg ;
/*
Gate Drive HS Register (address = 0x03h)
*/
typedef struct
{
uint16_t IDRIVEN_HS : 4;
uint16_t IDRIVEP_HS : 4;
uint16_t LOCK : 3;
uint16_t res : 5;
}Drv_GateHS_bit;
typedef struct
{
union
{
uint16_t data;
Drv_GateHS_bit gateHSRegObj;
};
} Drv_GateHS;
/*
Gate Drive LS Register (address = 0x04h)
*/
typedef struct
{
uint16_t IDRIVEN_LS : 4;
uint16_t IDRIVEP_LS : 4;
uint16_t TDRIVE : 2;
uint16_t CBC : 1;
uint16_t res : 5;
}Drv_GateLS_bit;
typedef struct
{
union
{
uint16_t data;
Drv_GateLS_bit gateLSRegObj;
};
} Drv_GateLS;
/*
OCP Control Register (address = 0x05h)
*/
typedef struct
{
uint16_t VDS_LVL : 4;
uint16_t OCP_DEG : 2;
uint16_t OCP_MODE : 2;
uint16_t DEAD_TIME : 2;
uint16_t TRETRY : 1;
uint16_t res : 5;
}Drv_OCP_bit;
typedef struct
{
union
{
uint16_t data;
Drv_OCP_bit ocpObj;
};
} Drv_OCP;
/*
CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
*/
typedef struct
{
uint16_t SEN_LVL : 2;
uint16_t CSA_CAL_C : 1;
uint16_t CSA_CAL_B : 1;
uint16_t CSA_CAL_A : 1;
uint16_t DIS_SEN : 1;
uint16_t CSA_GAIN : 2;
uint16_t LS_REF : 1;
uint16_t VREF_DIV : 1;
uint16_t CSA_FET : 1;
uint16_t res : 5;
}Drv_CSA_bit;
typedef struct
{
union
{
uint16_t data;
Drv_CSA_bit csaObj;
};
} Drv_CSA;
/*
Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
*/
typedef struct
{
uint16_t SEN_LVL : 1;
uint16_t RES : 10;
uint16_t res : 5;
}Drv_Cfg_bit;
typedef struct
{
union
{
uint16_t data;
Drv_Cfg_bit cfgObj;
};
} Drv_Cfg;
typedef struct
{
Drv_Cfg drvCfg_obj;
Drv_CSA drvCsa_obj;
Drv_OCP drvOcp_obj;
Drv_GateLS drvGateLS_obj;
Drv_GateHS drvGateHS_obj;
Fault_StatusReg1 faultStatusReg1_obj;
Fault_StatusReg2 faultStatusReg2_obj;
Drv_CtrlReg drvCtrl_obj;
}Stru_DRV835X;
extern Stru_DRV835X stru_DRV8353Obj;
typedef struct
{
// Driver Control Register (address = 0x02h)
uint8_t PWM_MODE;
// CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
uint8_t SEN_LVL;
uint8_t CSA_GAIN;
uint8_t VREF_DIV;
// OCP Control Register (address = 0x05h)
uint8_t VDS_LVL;
uint8_t OCP_DEG;
uint8_t OCP_MODE;
uint8_t DEAD_TIME;
//Gate Drive HS Register (address = 0x03h)
uint8_t IDRIVEP_HS;
uint8_t IDRIVEN_HS;
uint8_t LOCK;
// Gate Drive LS Register (address = 0x04h)
uint8_t IDRIVEN_LS;
uint8_t IDRIVEP_LS;
uint8_t TDRIVE;
uint8_t CBC;
} StruDRV835XCfgPara;
void DRV835X_Init(void);
void DRV835X_updateCfgPara( void );
void DRV835X_read_FaultStatusReg1(void);
void DRV835X_read_FaultStatusReg2(void);
#ifdef _cplusplus
}
#endif
#endif /* DRV835X_H */
3) drv_DRV835X_reg.h 文件
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : drv_DRV835X.h
* Description : DRV835X driver
******************************************************************************
* @attention
*
* COPYRIGHT: Copyright (c) 2025
* CREATED BY: ming fei.tang
* DATE: January 04th, 2025
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#ifndef __DRV_DRV835X_REG_H
#define __DRV_DRV835X_REG_H
#ifdef _cplusplus
extern "C"
{
#endif
#include "main.h"
/// Registers ///
#define FSR1 0x0 /// Fault Status Register 1
#define FSR2 0x1 /// Fault Status Register 2
#define DCR 0x2 /// Drive Control Register
#define HSR 0x3 /// Gate Drive HS Register
#define LSR 0x4 /// Gate Drive LS Register
#define OCPCR 0x5 /// OCP Control Register
#define CSACR 0x6 /// CSA Control Register
#define DFGCR 0x7 /// Driver Configuration Register
/// Drive Control Fields ///
#define DIS_CPUV_EN 0x0 /// Charge pump UVLO fault
#define DIS_CPUV_DIS 0x1
#define DIS_GDF_EN 0x0 /// Gate drive fauilt
#define DIS_GDF_DIS 0x1
#define OTW_REP_EN 0x1 /// Over temp warning reported on nFAULT/FAULT bit
#define OTW_REP_DIS 0x0
#define PWM_MODE_6X 0x0 /// PWM Input Modes
#define PWM_MODE_3X 0x1
#define PWM_MODE_1X 0x2
#define PWM_MODE_IND 0x3
#define PWM_1X_COM_SYNC 0x0 /// 1x PWM Mode synchronou rectification
#define PWM_1X_COM_ASYNC 0x1
#define PWM_1X_DIR_0 0x0 /// In 1x PWM mode this bit is ORed with the INHC (DIR) input
#define PWM_1X_DIR_1 0x1
/// Gate Drive HS Fields ///
#define LOCK_ON 0x6
#define LOCK_OFF 0x3
#define IDRIVEP_HS_10MA 0x0 /// Gate drive high side turn on current
#define IDRIVEP_HS_30MA 0x1
#define IDRIVEP_HS_60MA 0x2
#define IDRIVEP_HS_80MA 0x3
#define IDRIVEP_HS_120MA 0x4
#define IDRIVEP_HS_140MA 0x5
#define IDRIVEP_HS_170MA 0x6
#define IDRIVEP_HS_190MA 0x7
#define IDRIVEP_HS_260MA 0x8
#define IDRIVEP_HS_330MA 0x9
#define IDRIVEP_HS_370MA 0xA
#define IDRIVEP_HS_440MA 0xB
#define IDRIVEP_HS_570MA 0xC
#define IDRIVEP_HS_680MA 0xD
#define IDRIVEP_HS_820MA 0xE
#define IDRIVEP_HS_1000MA 0xF
#define IDRIVEN_HS_20MA 0x0 /// High side turn off current
#define IDRIVEN_HS_60MA 0x1
#define IDRIVEN_HS_120MA 0x2
#define IDRIVEN_HS_160MA 0x3
#define IDRIVEN_HS_240MA 0x4
#define IDRIVEN_HS_280MA 0x5
#define IDRIVEN_HS_340MA 0x6
#define IDRIVEN_HS_380MA 0x7
#define IDRIVEN_HS_520MA 0x8
#define IDRIVEN_HS_660MA 0x9
#define IDRIVEN_HS_740MA 0xA
#define IDRIVEN_HS_880MA 0xB
#define IDRIVEN_HS_1140MA 0xC
#define IDRIVEN_HS_1360MA 0xD
#define IDRIVEN_HS_1640MA 0xE
#define IDRIVEN_HS_2000MA 0xF
/// Gate Drive LS Fields : Gate Drive LS Register (address = 0x04h)
#define TDRIVE_500NS 0x0 /// Peak gate-current drive time
#define TDRIVE_1000NS 0x1
#define TDRIVE_2000NS 0x2
#define TDRIVE_4000NS 0x3
#define IDRIVEP_LS_10MA 0x0 /// Gate drive high side turn on current
#define IDRIVEP_LS_30MA 0x1
#define IDRIVEP_LS_60MA 0x2
#define IDRIVEP_LS_80MA 0x3
#define IDRIVEP_LS_120MA 0x4
#define IDRIVEP_LS_140MA 0x5
#define IDRIVEP_LS_170MA 0x6
#define IDRIVEP_LS_190MA 0x7
#define IDRIVEP_LS_260MA 0x8
#define IDRIVEP_LS_330MA 0x9
#define IDRIVEP_LS_370MA 0xA
#define IDRIVEP_LS_440MA 0xB
#define IDRIVEP_LS_570MA 0xC
#define IDRIVEP_LS_680MA 0xD
#define IDRIVEP_LS_820MA 0xE
#define IDRIVEP_LS_1000MA 0xF
#define IDRIVEN_LS_20MA 0x0 /// High side turn off current
#define IDRIVEN_LS_60MA 0x1
#define IDRIVEN_LS_120MA 0x2
#define IDRIVEN_LS_160MA 0x3
#define IDRIVEN_LS_240MA 0x4
#define IDRIVEN_LS_280MA 0x5
#define IDRIVEN_LS_340MA 0x6
#define IDRIVEN_LS_380MA 0x7
#define IDRIVEN_LS_520MA 0x8
#define IDRIVEN_LS_660MA 0x9
#define IDRIVEN_LS_740MA 0xA
#define IDRIVEN_LS_880MA 0xB
#define IDRIVEN_LS_1140MA 0xC
#define IDRIVEN_LS_1360MA 0xD
#define IDRIVEN_LS_1640MA 0xE
#define IDRIVEN_LS_2000MA 0xF
#define PWM_GIVER_ENABLE 0x1
#define PWM_GIVER_DISABLE 0x0
/// OCP Control Fields ///
#define TRETRY_4MS 0x0 /// VDS OCP and SEN OCP retry time
#define TRETRY_50US 0x1
#define DEADTIME_50NS 0x0 /// Deadtime
#define DEADTIME_100NS 0x1
#define DEADTIME_200NS 0x2
#define DEADTIME_400NS 0x3
#define OCP_LATCH 0x0 /// OCP Mode
#define OCP_RETRY 0x1
#define OCP_REPORT 0x2
#define OCP_NONE 0x3
#define OCP_DEG_2US 0x0 /// OCP Deglitch Time
#define OCP_DEG_4US 0x1
#define OCP_DEG_6US 0x2
#define OCP_DEG_8US 0x3
#define VDS_LVL_0_06 0x0
#define VDS_LVL_0_13 0x1
#define VDS_LVL_0_2 0x2
#define VDS_LVL_0_26 0x3
#define VDS_LVL_0_31 0x4
#define VDS_LVL_0_45 0x5
#define VDS_LVL_0_53 0x6
#define VDS_LVL_0_6 0x7
#define VDS_LVL_0_68 0x8
#define VDS_LVL_0_75 0x9
#define VDS_LVL_0_94 0xA
#define VDS_LVL_1_13 0xB
#define VDS_LVL_1_3 0xC
#define VDS_LVL_1_5 0xD
#define VDS_LVL_1_7 0xE
#define VDS_LVL_1_88 0xF
/// CSA Control Fields ///
#define CSA_FET_SP 0x0 /// Current sense amplifier positive input
#define CSA_FET_SH 0x1
#define VREF_DIV_1 0x0 /// Amplifier reference voltage is VREV/1
#define VREF_DIV_2 0x1 /// Amplifier reference voltage is VREV/2
#define CSA_GAIN_5 0x0 /// Current sensor gain
#define CSA_GAIN_10 0x1
#define CSA_GAIN_20 0x2
#define CSA_GAIN_40 0x3
#define DIS_SEN_EN 0x0 /// Overcurrent Fault
#define DIS_SEN_DIS 0x1
#define SEN_LVL_0_25 0x0 /// Sense OCP voltage level
#define SEN_LVL_0_5 0x1
#define SEN_LVL_0_75 0x2
#define SEN_LVL_1_0 0x3
#ifdef _cplusplus
}
#endif
#endif /* __DRV_DRV835X_REG_H */