``
module BCH_CHIEN #(
parameter BCH_T = 2 ,
parameter BCH_GF_M = 8 ,
parameter BCH_GF_ELM = 255,
parameter BCH_CHIEN_WIDTH = 16 , // number of roots to check for each cycle
parameter BCH_CHIEN_DEPTH = 16 // number of pipline depth (cycles) for chien search
)(
input clk ,
input rst_n ,
input [BCH_GF_M-1:0] sigma_1_idx , // from sigma
input [BCH_GF_M-1:0] sigma_2_idx , // from sigma
output [BCH_GF_M-1:0] tab_add1_idx_0, // table channel (sgm1a^0)
input [BCH_GF_M-1:0] tab_add1_0 ,
output [BCH_GF_M-1:0] tab_add2_idx_1, // table channel (sgm2a^0)
input [BCH_GF_M-1:0] tab_add2_0 ,
output [2BCH_GF_M-1:0] error_loc // to correction
);
// wire
wire [BCH_GF_ELM-1:0] [BCH_GF_M-1:0] add1; // 2548bit
wire [BCH_GF_ELM-1:0] [BCH_GF_M-1:0] add2; // 2548bit
wire [BCH_GF_ELM-1:0] [BCH_GF_M-1:0] sum ; // 2548bit
wire [BCH_GF_ELM-1:0] flag_has_error; // 254 * 1 bit
wire [BCH_GF_ELM-1:0] [1:0] ptr ; // 254 * 2 bit
wire [BCH_GF_ELM-1:0] [2*BCH_GF_M-1:0] error_location; // 254 * 16bit
genvar i;
genvar j;
// combinational
assign tab_add1_idx_0 = sigma_1_idx;
assign tab_add2_idx_0 = sigma_2_idx;
assign error_loc = error_location[BCH_GF_ELM-1]; //=error_location[254]
// pipline_1 a^0~a^15
assign add1 [0] = tab_add1_0;
assign add2 [0] = tab_add2_0;
assign sum [0] = add1[0] ^ add2[0];
assign flag_has_error[0] = (sum[0][BCH_GF_M-1:1] == 0) && sum[0][0] ? 1'b1:1'b0; // add3 is 0000,0001
assign ptr [0] = 2'b00;
assign error_location[0] = {(2*BCH_GF_M){1'b0}};
generate
for (i=1; i<BCH_CHIEN_WIDTH; i=i+1) begin // i=1~15
assign add1 [i] = !add1[i-1][BCH_GF_M-1] ? {add1[i-1][BCH_GF_M-2:0],1'b0} : // no overflow
{add1[i-1][BCH_GF_M-2:0],1'b0} ^ 8'b0001_1101 ; // overflow, right shift then XOR X^4+X^3+X^2+1
assign add2 [i] = !add2[i-1][BCH_GF_M-1] ? {add2[i-1][BCH_GF_M-2:0],1'b0} : // no overflow
{add2[i-1][BCH_GF_M-2:0],1'b0} ^ 8'b0001_1101 ; // overflow, right shift then XOR X^4+X^3+X^2+1
assign sum [i] = add1[i] ^ add2[i];
assign flag_has_error[i] = (sum[i][BCH_GF_M-1:1] == 0) && sum[i][0] ? 1'b1:1'b0; // add3 is 0000,0001
assign ptr [i] = flag_has_error[i-1] ? ptr[i-1]+2'b01 : ptr[i-1];
assign error_location[i][ BCH_GF_M-1 : 0] = (flag_has_error[i] && (ptr[i]==2'b00)) ? i : error_location[i-1][ BCH_GF_M-1 : 0];
assign error_location[i][2*BCH_GF_M-1:BCH_GF_M] = (flag_has_error[i] && (ptr[i]==2'b01)) ? i : error_location[i-1][2*BCH_GF_M-1:BCH_GF_M]; //if ptr[i] becomes 2'b10, then error has all been found
end
endgenerate
// pipeline_j a^16j+1 ~ a^16j+15
generate
for (j=1; j<BCH_CHIEN_DEPTH; j=j+1) begin // j=1~15, i=1~15
for (i=1; i<BCH_CHIEN_WIDTH; i=i+1) begin // 16*1+1~16*1+15, ..., 16*15+1~16*15+15
assign add1 [BCH_CHIEN_WIDTH*j+i] = !add1[BCH_CHIEN_WIDTH*j+i-1][BCH_GF_M-1] ? {add1[BCH_CHIEN_WIDTH*j+i-1][BCH_GF_M-2:0],1'b0} : // no overflow
{add1[BCH_CHIEN_WIDTH*j+i-1][BCH_GF_M-2:0],1'b0} ^ 8'b0001_1101 ; // overflow
assign add2 [BCH_CHIEN_WIDTH*j+i] = !add2[BCH_CHIEN_WIDTH*j+i-1][BCH_GF_M-1] ? {add2[BCH_CHIEN_WIDTH*j+i-1][BCH_GF_M-2:0],1'b0} : // no overflow
{add2[BCH_CHIEN_WIDTH*j+i-1][BCH_GF_M-2:0],1'b0} ^ 8'b0001_1101 ; // overflow
assign sum [BCH_CHIEN_WIDTH*j+i] = add1[BCH_CHIEN_WIDTH*j+i] ^ add2[BCH_CHIEN_WIDTH*j+i];
assign flag_has_error[BCH_CHIEN_WIDTH*j+i] = (sum[BCH_CHIEN_WIDTH*j+i][BCH_GF_M-1:1] == 0) && sum[BCH_CHIEN_WIDTH*j+i][0] ? 1'b1:1'b0; // add3 is 0000,0001
assign ptr [BCH_CHIEN_WIDTH*j+i] = flag_has_error[BCH_CHIEN_WIDTH*j+i-1] ? ptr[BCH_CHIEN_WIDTH*j+i-1]+2'b01 : ptr[BCH_CHIEN_WIDTH*j+i-1];
assign error_location[BCH_CHIEN_WIDTH*j+i][ BCH_GF_M-1 : 0] = (flag_has_error[BCH_CHIEN_WIDTH*j+i] && (ptr[BCH_CHIEN_WIDTH*j+i]==2'b00)) ? i : error_location[BCH_CHIEN_WIDTH*j+i-1][ BCH_GF_M-1 : 0];
assign error_location[BCH_CHIEN_WIDTH*j+i ][2*BCH_GF_M-1:BCH_GF_M] = (flag_has_error[BCH_CHIEN_WIDTH*j+i] && (ptr[BCH_CHIEN_WIDTH*j+i]==2'b01)) ? i : error_location[BCH_CHIEN_WIDTH*j+i-1][2*BCH_GF_M-1:BCH_GF_M];
end
end
endgenerate
// sequential logic
generate
for (j=1; j<BCH_CHIEN_DEPTH; j=j+1) begin
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
add1 [BCH_CHIEN_WIDTH*j] <= 'b0;
add2 [BCH_CHIEN_WIDTH*j] <= 'b0;
sum [BCH_CHIEN_WIDTH*j] <= 'b0;
flag_has_error[BCH_CHIEN_WIDTH*j] <= 'b0;
ptr [BCH_CHIEN_WIDTH*j] <= 'b0;
error_location[BCH_CHIEN_WIDTH*j] <= 'b0;
end else begin
add1 [BCH_CHIEN_WIDTH*j] <= !add1[BCH_CHIEN_WIDTH*j-1][BCH_GF_M-1] ? {add1[BCH_CHIEN_WIDTH*j-1][BCH_GF_M-2:0],1'b0} : // no overflow
{add1[BCH_CHIEN_WIDTH*j-1][BCH_GF_M-2:0],1'b0} ^ 8'b0001_1101 ; // overflow
add2 [BCH_CHIEN_WIDTH*j] <= !add2[BCH_CHIEN_WIDTH*j-1][BCH_GF_M-1] ? {add2[BCH_CHIEN_WIDTH*j-1][BCH_GF_M-2:0],1'b0} : // no overflow
{add2[BCH_CHIEN_WIDTH*j-1][BCH_GF_M-2:0],1'b0} ^ 8'b0001_1101 ; // overflow
sum [BCH_CHIEN_WIDTH*j] <= add1[BCH_CHIEN_WIDTH*j] ^ add2[BCH_CHIEN_WIDTH*j];
flag_has_error[BCH_CHIEN_WIDTH*j] <= (sum[BCH_CHIEN_WIDTH*j][BCH_GF_M-1:1] == 0) && sum[BCH_CHIEN_WIDTH*j][0] ? 1'b1:1'b0; // add3 is 0000,0001
ptr [BCH_CHIEN_WIDTH*j] <= flag_has_error[BCH_CHIEN_WIDTH*j-1] ? ptr[BCH_CHIEN_WIDTH*j-1]+2'b01 : ptr[BCH_CHIEN_WIDTH*j-1];
error_location[BCH_CHIEN_WIDTH*j][ BCH_GF_M-1 : 0] <= (flag_has_error[BCH_CHIEN_WIDTH*j] && (ptr[BCH_CHIEN_WIDTH*j]==2'b00)) ? i : error_location[BCH_CHIEN_WIDTH*j-1][ BCH_GF_M-1 : 0];
error_location[BCH_CHIEN_WIDTH*j][2*BCH_GF_M-1:BCH_GF_M] <= (flag_has_error[BCH_CHIEN_WIDTH*j] && (ptr[BCH_CHIEN_WIDTH*j]==2'b01)) ? i : error_location[BCH_CHIEN_WIDTH*j-1][2*BCH_GF_M-1:BCH_GF_M];
end
end
end
endgenerate
endmodule
``
标签：BCH,ELM,GF,算法,tab,error,设计,assign From： https://www.cnblogs.com/sjtu-zsj-990702/p/18426840