标签：A15 汇编 r0 setup BSP vector mode c0 p15
MSR CPSR_c, #Mode_SVC | I_Bit | F_Bit // SVC mode
// setup vector mode
/*BIT[13]:
0 ：选择低端异常中断向量 0x0~0x1c
1 ：选择高端异常中断向量0xffff0000~ 0xffff001c*/
MRC p15, 0, r0, c1, c0, 0 // Read Control Register
BIC r0, r0, #(1 << 13) // use 0x00000000 address vectorַַ
MCR p15, 0, r0, c1, c0, 0 // Write Control Register
// setup vector base
LDR r0, =Vectors
MCR p15, 0, r0, c12, c0, 0 // Write Secure or Non-secure Vector Base Address
/*
* Invalidate L1 I/D
*/
mov r0, #0 @ set up for MCR
/* BY BSP : uboot do these in v7_inval_tlb
MCR p15, 0, r0, c8, c5, 0 // ITLBIALL - Invalidate entire Instruction TLB
MCR p15, 0, r0, c8, c6, 0 // DTLBIALL - Invalidate entire Data TLB
*/
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
/*
* disable MMU stuff and caches
*/
//BSP only set bit:0 1 2 11 12 to zero
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
#endif
mcr p15, 0, r0, c1, c0, 0
//-------------------------above uboot,below bsp-------------------------
// enable multicore coherent notice //enable_smp
MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
MOV r1, r0
ORR r0, r0, #0x040 // Set bit 6
CMP r0, r1
MCRNE p15, 0, r0, c1, c0, 1 // Write ACTLR
ISB
/*TM: ACTLR
MRC p15, 0, r0, c1, c0, 1
orr r0,r0,#0x40
MCR p15, 0, r0, c1, c0, 1
UBOOT:
ENTRY(psci_disable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
bic r0, r0, #(1 << 6) @ Clear SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
dsb
bx lr
ENDPROC(psci_disable_smp)
.weak psci_disable_smp
ENTRY(psci_enable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
orr r0, r0, #(1 << 6) @ Set SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
bx lr
ENDPROC(psci_enable_smp)
.weak psci_enable_smp
*/
// setup domain
MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register
LDR r0, =0x55555555 // Initialize every domain entry to b01 (client)
MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register
////////////////////////////////////////////////
// enable vfp
MOV r0, #0x00F00000 // clear ASEDIS, enable cp10/cp11 access
MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR)
ISB
MOV r0, #0x40000000
VMSR FPEXC, r0 // Write FPEXC register, EN bit set
ISB
//most done by OS system:
// init mmu
// enable mmu & cache
// setup vector base
LDR r0, =Vectors
MCR p15, 0, r0, c12, c0, 0 // Write Secure or Non-secure Vector Base Address
////////////////////////////////////////////////
// setup vector mode
MRC p15, 0, r0, c1, c0, 0 // Read Control Register
BIC r0, r0, #(1 << 13) // use 0x00000000 address vectorַַ
MCR p15, 0, r0, c1, c0, 0 // Write Control Register
////////////////////////////////////////////////
// enable multicore coherent notice
MRC p15, 0, r0, c1, c0, 1 // Read ACTLR
MOV r1, r0
ORR r0, r0, #0x040 // Set bit 6
CMP r0, r1
MCRNE p15, 0, r0, c1, c0, 1 // Write ACTLR
ISB
////////////////////////////////////////////////
// disable mmu and cache
MRC p15, 0, r0, c1, c0, 0 // Read CP15 System Control register
BIC r0, r0, #(0x1 << 12) // Clear I, bit 12, to disable I Cache
BIC r0, r0, #(0x1 << 11) // Clear Z, bit 11, to disable branch prediction
BIC r0, r0, #(0x1 << 2) // Clear C, bit 2, to disable D Cache
BIC r0, r0, #(0x1 << 1) // Clear A, bit 1, to disable strict alignment fault checking
BIC r0, r0, #0x1 // Clear M, bit 0, to disable MMU
MCR p15, 0, r0, c1, c0, 0 // Write CP15 System Control register
ISB
////////////////////////////////////////////////
// setup domain
MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register
LDR r0, =0x55555555 // Initialize every domain entry to b01 (client)
MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register
////////////////////////////////////////////////
// enable vfp
MOV r0, #0x00F00000 // clear ASEDIS, enable cp10/cp11 access
MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR)
ISB
MOV r0, #0x40000000
VMSR FPEXC, r0 // Write FPEXC register, EN bit set
ISB
////////////////////////////////////////////////
// multi-core different init branch
MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register
ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field
CMP r0, #0
BEQ core_0_init
B core_1_init
.global core_0_init
core_0_init:
////////////////////////////////////////////////
//setup stack
LDR r1, =_core0_stack_top_
MSR CPSR_c, #Mode_IRQ | I_Bit | F_Bit // IRQ mode
MOV sp, r1
SUB r1, #4096
MSR CPSR_c, #Mode_FIQ | I_Bit | F_Bit // FIQ mode
MOV sp, r1
SUB r1, #256
MSR CPSR_c, #Mode_ABT | I_Bit | F_Bit // ABT mode
MOV sp, r1
SUB r1, #256
MSR CPSR_c, #Mode_UNDEF | I_Bit | F_Bit // UNDEF mode
MOV sp, r1
SUB r1, #256
MSR CPSR_c, #Mode_SYS | I_Bit | F_Bit // SYS mode
MOV sp, r1
SUB r1, #2048
MSR CPSR_c, #Mode_SVC | I_Bit | F_Bit // SVC mode
MOV sp, r1
////////////////////////////////////////////////
// init branch predictor
MOV r0, #0x0
MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array
////////////////////////////////////////////////
// init cache
MOV r0, #0
MCR p15, 0, r0, c7, c5, 0 // Invalidate entire instruction cache
.if (DCACHE_INVALID==1)
.if (ASSEMBLE_PRINT==1)
LDR r0, =msg_cache_invalid
BL print_msg
.endif
MOV r0, #0 // invalidate dcache
BL arm_all_dcache_operation
.endif
////////////////////////////////////////////////
// init TLB
MOV r0, #0x0
MCR p15, 0, r0, c8, c5, 0 // ITLBIALL - Invalidate entire Instruction TLB
MCR p15, 0, r0, c8, c6, 0 // DTLBIALL - Invalidate entire Data TLB
MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire Unified TLB
////////////////////////////////////////////////
// clear bss
.if (ASSEMBLE_PRINT==1)
LDR r0, =msg_clear_bss
BL print_msg
.endif
MOV r2, #0x0
MOV r3, #0x0
MOV r4, #0x0
MOV r5, #0x0
MOV r6, #0x0
MOV r7, #0x0
MOV r8, #0x0
MOV r9, #0x0
LDR r0, =_bss_start_
LDR r1, =_bss_end_
loop_clear_bss:
STMIA r0!, {r2-r9}
CMP r0, r1
BCC loop_clear_bss
DSB
////////////////////////////////////////////////
// init mmu
LDR r0, =(MMU_S1_NL_WT_RAWA<<24) | (MMU_S1_NL_NCE<<16) | (MMU_S1_DEV<<8) | MMU_S1_SGO
MCR p15, 0, r0, c10, c2, 0 // write MAIR0
LDR r0, =(MMU_S1_NL_WB_NA<<16) | (MMU_S1_NL_WB_RAWA<<8) | MMU_S1_NL_WT_NA
MCR p15, 0, r0, c10, c2, 1 // write MAIR1
LDR r0, =0x80000000 // enable EAE, non shareable, non cacheable, only use TTBR0
MCR p15, 0, r0, c2, c0, 2 // write TTBCR
ISB
LDR r0, =_mmu_l1_base_
LDR r1, =0 // table high address[39:32]=0, ASID=0
MCRR p15, 0, r0, r1, c2 // write 64-bit TTBR0
BL setup_mmu_l2_table_base
////////////////////////////////////////////////
// enable mmu
DSB
ISB
MRC p15, 0, r0, c1, c0, 0 // Read CP15 System Control register
ORR r0, r0, #0x1 // Set M bit 0 to enable MMU
MCR p15, 0, r0, c1, c0, 0 // Write CP15 System Control register
ISB
////////////////////////////////////////////////
// enable cache
MRC p15, 0, r0, c1, c0, 0 // Read System Control Register
ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache
//ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache
ORR r0, r0, #(0x1 << 11) // Set Z bit 11 to enable branch prediction
MCR p15, 0, r0, c1, c0, 0 // Write System Control Register
ISB
////////////////////////////////////////////////
// wake core1
//SEV
////////////////////////////////////////////////
// branch to main program
LDR r12, =core_0_main
BX r12
标签：A15,
汇编,
r0,
setup,
BSP,
vector,
mode,
c0,
p15
From： https://www.cnblogs.com/solo666/p/18264331