SystemC & TLM-2.0 - SystemC vs SystemVerilog

What is the difference between System C and SystemVerilog

System C is used primarily as a modeling language particularly for virtual platform modeling whereas system verilog is used mainly 50 chable Hardware verification. I'm going to dive down into both systems the answers to go up and describe each of them a little more detail for you.

Reasons for using System C

there are some great reasons for using System C. System C has some open source proof-of-concept simulator that only requires a C++ compiler to run and that makes it very flexible with respect to platforms and licensing it means that you can run a system c model if you simply have a C++ compiler available. EDA tool vendors then able to add further value to System C by implementing smart features within their tools System C. System C also robust amateur I Triple E standard has been in existence for several years now because it's just C++. it's a sports very easy integration with almost any software product or modeling product. System C also because it's based on C++ gives soft software engineers and system engineers very easy access to EDA technology and models so they might not.

Transaction-Level Modeling

otherwise have System C is usually used for transaction level modeling. transaction level modeling you can think of as an abstraction level that's above register transfer level now register transfer level all communication is done by pin wiggling so in order for to register transfer level blocks to communicate you need typically to have an event on each individual signal connecting those two blocks together and lots of events adds up to slow simulation contrast that with a transaction communication between blocks in a transaction level model is achieved using simple function calls then replacing lots of pin wiggling with single function calls gives a dramatic speed-up in simulation somewhere between 100x and 10000x is typical and that's worth having.

Typical Use Case : Virtual Platform

the usual use case the transaction level modeling of these days is building virtual platform models of complex system on chips these are systems that would typically include multiple processor course multiple software stacks multiple buses and bridges between those buses and also many many digital and analog Hardware IP blocks that all have to be integrated together and the challenge is to obtain models for all of these various bits of IP in such a way that they could work in a fast efficient simulation environment and that's what transaction little bottler consistency enables.

Reasons for using TLM / System C

so transaction level models very often start life being created by system architects or people interested in performance modeling in order to build fast executable bottleneck associate. those same models can then be handed off to software development groups and can be used to develop application software and firmware because they're fast enough and available early enough to enable that to happen the very same bodies can then be handed down to Hardware verification groups where they can be used within an HDL test bench as goal model a reference model of the designer to test.

What is SystemVerilog

so I've said a few words about System C let's now explore SystemVerilog in just a little bit more detail SystemVerilog has been touted as the world's first HDVL or hardware designed and verification language. you can also think of it as son of Verilog the latest in the verilog heritage. SystemVerilog speeches the RTL design for assertions and in particular for verification. so explore each of those areas now.

Features

for design SystemVerilog offers a number of significant RTL improvements he offers a very concise coding style without the need to catch RTL code in a very straightforward way and also offer synthesis aware syntax so that the HDL coding can better reflect your design intent system Verilog also offers interesting features for parameterization and generate which match many of the features that VHDL users have enjoyed for many years now and even go beyond what the VHDL offers in those areas on the assertions side there's a specific subset of system brakeness SVA. SystemVerilog assertions and for verification SystemVerilog offers a whole raft of language improvements it's got a new set of programming language features which are based on C. so there are C like data types and see like statements so if you're familiar with the control structures and the data types in C. you'll get home this is develop SystemVerilog. SystemVerilog paranthas a variety of dedicated testbench features so that you can express your testbench intent very explicitly in SystemVerilog. it also has a complete object-oriented programming language with its own flavor of class similar to classes in C++ and SystemVerilog has a number of features to support constrained random verification and those features build on the classes in SystemVerilog. finally SystemVerilog has a really cool feature which is the DPI or direct programming language interface the DPI is a very lightweight interface that enables you to call functions whose SystemVerilog and SystemVerilog functions and tasks from C and that's very convenient.

Constrained Random Verification

let's dive down into constrained random verification and little bit detail because this is arguably the number one reason why our customers are making use assistive SystemVerilog today. constrained random verification involves exercising a design under test using random test vectors and you need to do three particular things to make random stimulus useful and tractable. the first thing is to automatically check the results of simulation it's that good waveforms if your simulation stimulus is random of course SystemVerilog enables that with SVA in SystemVerilog assertions. the second thing that you need to do is to answer the question are we done and that's done using a set of features for collecting functional coverage. so functional coverage provides a measure of how much simulation has been performed and finally with random stimulus those random vectors need to be directed in order to explore corner cases in the design and that's done using a set of constraint features and SystemVerilog.

Multiple Languages

but in all this together we see our customers making increased use of mixed language environments in fact using multiple languages or design projects is pretty much the norm now for the most complex designs. so hardware designs still done largely in VHDL or Verilog so dedicated hardware design groups make use of the HDL apparel of capturing the RTL code testbenches may also be VHDL and Verilog or they might make use of one of a number of more specialized testbench languages. SystemVerilog is a great example of that. if System C is typically used to bring in a gold reference model. so a transaction level model of the design under test might have been created early or in the design flow may be used for software development and can then be brought into the hardware test vectors ago on a reference model so System C is used for modeling particularly in the software development and architectural exploration SystemVerilog is used for little big smart constrained random testbenches an RTL coding is typically done in good old-fashioned VHDL available.