1.进阶要求
➢ 十字路分为主干道Highway和乡村公路Farmroad；
➢ 路口的检测器C，没有检测到Farmroad上有等候的车子，Highway上的交通灯（HL）保持为绿灯；
➢ C检测到Farmroad上有车后HL再保持一段时间（例如30秒）才通过黄灯（例如3秒）变为红灯，同时 Farmroad上的交通灯（FL）从红灯变为绿灯；
➢ Farmroad上的绿灯只能在C检测有车的情况下才能保持，但是最多只能持续一段时间（例如30秒），然后 通过黄灯转为红灯，同时HL变为绿灯。
➢ 使用板载的LED灯代表交通灯上的红、黄、绿灯，两块数码管分别显示HL的绿灯最后15秒倒计时和黄灯3 秒倒计时以及FL的黄灯3秒倒计时；
2.控制要求
➢交通灯2有如下状态：
• H_green（主干道绿灯状态）
• H_green_wait（主干道绿灯倒计时 30秒状态）
• H_yellow（主干道黄灯状态）
• F_green（乡村公路绿灯状态）
• F_yellow（乡村公路黄灯状态
➢进阶交通灯比基础交通灯多了一个状态
3.状态转换图表
状态转换图
相较于之前的交通灯，这里多了一个检测乡村路段有无机动车的情况，若有车，则与之前一样，若没有，则城市路段一直绿灯通行，乡村路段一直红灯，所以只要对计时器和交通程序进行略微调整即可
4.交通灯代码
module traffic2(
input clk_1,
input reset,
input[7:0] counter_33, //33秒计数器
input c,
output reg Start_timer_33, //开始计数信号
output reg [1:0] H_display_en, //横向道路倒计时显示使能
output reg [7:0] H_count, //横向道路倒计时数值
output reg [1:0] V_display_en, //纵向道路倒计时显示使能
output reg [7:0] V_count, //纵向道路倒计时数值
output reg H_light_green, //横向绿灯
output reg H_light_yellow, //横向黄灯
output reg H_light_red, //横向红灯
output reg V_light_green, //纵向绿灯
output reg V_light_yellow, //纵向黄灯
output reg V_light_red //纵向红灯
);
parameter H_green = 5'b00001;
parameter H_yellow = 5'b00010;
parameter V_green = 5'b00100;
parameter V_yellow = 5'b01000;
parameter H_green_wait = 5'b10000;
parameter YES = 1'b1;
parameter NO = 1'b0;
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter DISPLAY_ON = 2'b00;
parameter DISPLAY_OFF = 2'b11;
reg [3:0] state;
reg [3:0] next_state;
//第一个进程，同步时序always模块，格式化描述次态寄存器转移到现态寄存器；
always@(posedge clk_1 ,negedge reset)
begin
if(c)
begin
if(!reset)
state <= H_green;
else
state <= next_state;
end
else
state <= H_green_wait;
end
end
//第二个进程，同步时序always模块，描述次态寄存器的状态转移条件
always@ (posedge clk_1 ,negedge reset)
if(!reset)
next_state <= H_green;
else
begin
case(next_state)
H_green:
if(counter_33 == 4)
next_state <= H_yellow;
else
next_state <= H_green;
H_yellow:
if(counter_33 == 1)
next_state <= V_green;
else
next_state <= H_yellow;
V_green:
if(counter_33 == 4)
next_state <= V_yellow;
else
next_state <= V_green;
V_yellow:
if(counter_33 == 1)
next_state <= H_green;
else
next_state <= V_yellow;
default:
next_state <= H_green;
endcase
end
//第三个进程，同步时序always块，格式化描述次态寄存器的输出
always@(posedge clk_1 ,negedge reset)
if(!reset)
begin
H_light_green <= ON;
H_light_yellow <= OFF;
H_light_red <= OFF;
V_light_green <= OFF;
V_light_yellow <= OFF;
V_light_red <= ON;
H_count <= 4'b0000;
V_count <= 4'b0000;
H_display_en <= DISPLAY_OFF;
V_display_en <= DISPLAY_OFF;
Start_timer_33 <= YES;
end
else
begin
case(next_state)
H_green:
begin
H_light_green <= ON;
H_light_yellow <= OFF;
H_light_red <= OFF;
V_light_green <= OFF;
V_light_yellow <= OFF;
V_light_red <= ON;
Start_timer_33 <= NO;
if(counter_33 <= 18 && counter_33 >= 4)
begin
H_count <= counter_33 - 3;
H_display_en <= DISPLAY_ON;
end
else
H_display_en <= DISPLAY_OFF;
if(counter_33 <= 15 && counter_33 >= 1)
begin
V_count <= counter_33;
V_display_en <= DISPLAY_ON;
end
else
V_display_en <= DISPLAY_OFF;
end
H_yellow:
begin
H_light_green <= OFF;
H_light_yellow <= ON;
H_light_red <= OFF;
V_light_green <= OFF;
V_light_yellow <= OFF;
V_light_red <= ON;
if(counter_33 <= 3 && counter_33 >= 1)
begin
H_count <= counter_33;
H_display_en <= DISPLAY_ON;
end
else
H_display_en <= DISPLAY_OFF;
if(counter_33 <= 15 && counter_33 >= 1)
begin
V_count <= counter_33;
V_display_en <= DISPLAY_ON;
end
else
V_display_en <= DISPLAY_OFF;
if(counter_33 == 1)
Start_timer_33 <= YES;
else
Start_timer_33 <= NO;
end
V_green:
begin
H_light_green <= OFF;
H_light_yellow <= OFF;
H_light_red <= ON;
V_light_green <= ON;
V_light_yellow <= OFF;
V_light_red <= OFF;
Start_timer_33 <= NO;
if(counter_33 <= 18 && counter_33 >= 4)
begin
V_count <= counter_33 - 3;
V_display_en <= DISPLAY_ON;
end
else
V_display_en <= DISPLAY_OFF;
if(counter_33 <= 15 && counter_33 >= 1)
begin
H_count <= counter_33;
H_display_en <= DISPLAY_ON;
end
else
H_display_en <= DISPLAY_OFF;
end
V_yellow:
begin
H_light_green <= OFF;
H_light_yellow <= OFF;
H_light_red <= ON;
V_light_green <= OFF;
V_light_yellow <= ON;
V_light_red <= OFF;
if(counter_33 <= 3 && counter_33 >= 1)
begin
V_count <= counter_33;
V_display_en <= DISPLAY_ON;
end
else
V_display_en <= DISPLAY_OFF;
if(counter_33 <= 15 && counter_33 >= 1)
begin
H_count <= counter_33;
H_display_en <= DISPLAY_ON;
end
else
H_display_en <= DISPLAY_OFF;
if(counter_33 == 1)
Start_timer_33 <= YES;
else
Start_timer_33 <= NO;
end
H_green_wait:
begin
H_light_green <= ON;
H_light_yellow <= OFF;
H_light_red <= OFF;
V_light_green <= OFF;
V_light_yellow <= OFF;
V_light_red <= ON;
Start_timer_33 <= NO;
if(counter_33 == 33)
begin
H_count <= counter_33;
H_display_en <= DISPLAY_ON;
end
else
H_display_en <= DISPLAY_OFF;
end
default:
begin
H_light_green <= ON;
H_light_yellow <= OFF;
H_light_red <= OFF;
V_light_green <= OFF;
V_light_yellow <= OFF;
V_light_red <= ON;
H_count <= 4'b0000;
V_count <= 4'b0000;
H_display_en <= DISPLAY_OFF;
V_display_en <= DISPLAY_OFF;
Start_timer_33 <= YES;
end
endcase
end
endmodule5.计数器
module counter(
input clk_1,
input reset,
input Start_timer_33,
output reg[7:0] counter_33
);
always@(posedge clk_1, negedge reset)
if(c)
begin
if(!reset)
counter_33 <= 32;
else if(Start_timer_33)
counter_33 <= 32;
else
counter_33 <= counter_33 -1;
end
else
counter_33 <= 33;
endmodule6.顶层代码
module traffic2_top(
input clk,
input reset,
input c,
output H_light_green,
output H_light_yellow,
output H_light_red,
output V_light_green,
output V_light_yellow,
output V_light_red,
output [3:0] an,
output [7:0] sseg,
output [7:0] counter
);
wire clk_200;
wire clk_1;
clk_div U1(
.clk_100M(clk),
.reset(reset),
.clk_200(clk_200),
.clk_1(clk_1)
);
wire Start_timer_33;
wire [7:0] counter_33;
counter U2(
.clk_1(clk_1),
.reset(reset),
.c(c),
.Start_timer_33(Start_timer_33),
.counter_33(counter_33)
);
wire [1:0] H_display_en;
wire [1:0] V_display_en;
wire [3:0] H_count;
wire [3:0] V_count;
traffic2 U3(
.clk_1(clk_1),
.reset(reset),
.c(c),
.counter_33(counter_33),
.Start_timer_33(Start_timer_33),
.H_count(H_count),
.V_count(V_count),
.H_light_green(H_light_green),
.H_light_yellow(H_light_yellow),
.H_light_red(H_light_red),
.V_light_green(V_light_green),
.V_light_yellow(V_light_yellow),
.V_light_red(V_light_red)
);
wire [7:0] H_bcd;
wire [7:0] V_bcd;
bin2bcd U4(
.data_bin(H_count),
.data_bcd(H_bcd)
);
bin2bcd U5(
.data_bin(V_count),
.data_bcd(V_bcd)
);
bin2bcd U6(
.data_bin(counter_33),
.data_bcd(counter)
);
display U7(
.clk_200(clk_200),
.hex3(H_bcd[7:4]),
.hex2(H_bcd[3:0]),
.hex1(V_bcd[7:4]),
.hex0(V_bcd[3:0]),
.display_en({H_display_en,V_display_en}),
.an(an),
.sseg(sseg)
);
endmodule