SystemVerilog Packed Arrays
SystemVerilog 中有两种类型的数组- packed array 和 unpacked array。
packed array用于引用在变量名称之前声明的维度。
bit [3:0] data; // Packed array or vector
logic queue [9:0]; // unpacked array
packed array保证表示为一组连续的位。它们只能用于单位数据类型(如、和其他递归packed array)组成。bit
logic
Single Dimensional Packed Arrays
一维压缩数组也成为向量
。
module tb;
bit [7:0] m_data; // A vector or 1D packed array
initial begin
// 1. Assign a value to the vector
m_data = 8'hA2;
// 2. Iterate through each bit of the vector and print value
for (int i = 0; i < $size(m_data), i++) begin
$display ("m_data[%0d] = %b", i, m_data[i]);
end
end
endmodule
Muultidimensional Packed Arrays
多维打包数组仍然是一组连续的位,但也被分割成更小的组。
Example #1
下面显示的代码声明一个占用32位或4个字节的2D打包数组,并循环访问段并打印其值。
module tb;
bit [3:0][7:0] m_data; // A MDA, 4 bytes
initial begin
// 1. Assign a value to the MDA
m_data = 32'hface_cafe;
$display ("m_data = 0x%0h", m_data);
// 2. Iterate through each segment of the MDA and print value
for (int i = 0; i < $size(m_data); i++) begin
$display("m_data[%0d] = %b (0x%0h)", i, m_data[i], m_data[i]);
end
end
endmodule
模拟日志
ncsim> run
m_data = 0xfacecafe
m_data[0] = 11111110 (0xfe)
m_data[1] = 11001010 (0xca)
m_data[2] = 11001110 (0xce)
m_data[3] = 11111010 (0xfa)
ncsim: *W,RNQUIE: Simulation is complete.
Example #2
现在让我们看一个3D packed array
module tb;
bit [2:0][3:0][7:0] m_data; // An MDA, 12 bytes
initial begin
// 1. Assign a value to the MDA
m_data[0] = 32'hface_cafe;
m_data[1] = 32'h1234_5678;
m_data[2] = 32'hc0de_fade;
// m_data gets a packed value
$display ("m_data = 0x%0h", m_data);
// 2. Iterate through each segment of the MDA and print value
foreach (m_data[i]) begin
$display ("m_data[%0d] = 0x%0h", i, m_data[i]);
foreach (m_data[i][j]) begin
$display ("m_data[%0d][%0d] = 0x%0h", i, j, m_data[i][j]);
end
end
end
endmodule
模拟日志
ncsim> run
m_data = 0xc0defade12345678facecafe
m_data[2] = 0xc0defade
m_data[2][3] = 0xc0
m_data[2][2] = 0xc0
m_data[2][1] = 0xc0
m_data[2][0] = 0xc0
m_data[1] = 0x12345678
m_data[1][3] = 0x12
m_data[1][2] = 0x34
m_data[1][1] = 0x56
m_data[1][0] = 0x78
m_data[1] = 0x12345678
m_data[0][3] = 0xfa
m_data[0][2] = 0xce
m_data[0][1] = 0xca
m_data[0][0] = 0xfe
ncsim: *W,RNQUIE: Simulation is complete.
标签:begin,end,--,value,Arrays,SystemVerilog,array,data,packed
From: https://www.cnblogs.com/sys-123456/p/18170397