SystemVerilog 'integer' and 'byte'
除了 verilog 支持的所有数据类型外，SystemVerilog 还具有许多其他2-state的数据类型。现代testbench中最常用的数据类型是bit、int、logic和byte。
integer
整数是没有小数部分的数字，换句话说，它们是整数。SystemVerilog有三种新的signed数据类型保存整数值，每种类型都有不同的大小。数据的范围是-32768到32767。可以使用关键字和显式定义符号。此外，他们也可以通过铸造相互转换。shortint longint signed unsigned
// ubyte is converted to signed type and assigned to si
si = signed' (ubyte);
Signed
默认情况下，整数变量本质上是有符号的，因此可以同时保存正值和负值。
module tb;
// By default int data types are signed which means that MASB is the sign bit and the integer variables can also store negative numbers
shortint var_a;
int var_b;
longint var_c;
initial begin
// Print initial values of the integer variables
$display ("Sizes var_a=%0d var_b=%0d var_c=%0d", $bits(var_a), $bits(var_b), $bits(var_c));
// Assign the maximum value for each of the variables
// MSB of each variable represents the sign bit and is set to 0
// Reset of the bit positions are filled with 1 and hence you get the maximum value that these variables can hold
#1 var_a = 'h7FFF;
var_b = 'h7FFF_FFFF;
var_c = 'h7FFF_FFFF_FFFF_FFFF;
// When added a 1, the sign changes to negative because this is a signed varible
#1 var_a += 1； // Value becomes 'h8000 => which is a rollover from + sign to - sign
var_b += 1； // Value becomes 'h8000_0000 => which is a rollover from + sign to - sign
var_c += 1；
end
// Start a monitor to print out values of each varibles as they change
initial
$monitor (" var_a=%0d var_b=%0d var_c=%0d", var_a, var_b, var_c);
endmodule
系统任务返回变量中的位数。请注意，var_a、var_b和var_c会滚动到消极的一面。$bits
Simulation Log
Sizes var_a=16 var_b=32 var_c=64
var_a=0 var_b=0 var_c=0
var_a=32767 var_b=2147483647 var_c=9223372036854775807
var_a=-32768 var_b=-2147483648 var_c=-9223372036854775808
Unsigned
我们将上面示例中声明的变量更改为unsigned类型，并查看结果。
module tb;
// In this case, we are going to make it unsigneed which means that MSB no longer holds the sign information and hence these variables can only store positive values
shortint var_a;
int var_b;
longint var_c;
initial begin
// Print initial values of the integer variables
$display ("Sizes var_a=%0d var_b=%0d var_c=%0d", $bits(var_a), $bits(var_b), $bits(var_c));
// Assign the maximum value for each of the variables
// MSB of each variable represents the sign bit and is set to 0
// Reset of the bit positions are filled with 1 and hence you get the maximum value that these variables can hold
#1 var_a = 'h7FFF;
var_b = 'h7FFF_FFFF;
var_c = 'h7FFF_FFFF_FFFF_FFFF;
// When added a 1, value rolls over to 0
#1 var_a += 1； // Value becomes 'h0
var_b += 1； // Value becomes 'h0
var_c += 1；
end
// Start a monitor to print out values of each varibles as they change
initial
$monitor (" var_a=%0d var_b=%0d var_c=%0d", var_a, var_b, var_c);
endmodule
Simulation Log
Sizes var_a=16 var_b=32 var_c=64
var_a=0 var_b=0 var_c=0
var_a=65535 var_b=4294967295 var_c=18446744073709551615
var_a=0 var_b=0 var_c=0
byte
A 是整数的更短版本，大小为 8 位。默认情况下，byte是一个有符号变量，并且具有与上一节中描述的整数相同的属性。
module tb;
byte s_byte; // by default byte is signed
byte unsigned u_byte; // Byte is set to unsigned
initial begin
$display ("Size s_byte=%0d, u_byte=%0d", $bits(s_byte), $bits(u_byte));
// Assign the "assumed" maximum value to both variables
#1 s_byte = 'h7F;
u_byte = 'h7F;
// Increment by 1, and see that a_byte rolled over to negative because byte is signed by default. u_byte keeps increasing because it is unsigned and can go upto 255
#1 s_byte += 1;
u_byte += 1;
// Assign 255 (8'hFF) to u_byte -> this is the max value it can hold
#1 u_byte = 'hFF;
// Add 1 and see that it rolls over to 0
#1 u_byte += 1;
end
initial begin
$monitor (" [%0t ns] s_byte=%0d u_byte=%0d", $time, s_byte, u_byte);
end
endmodule
Simulation Log
ncsim> run
Size s_byte=8, u_byte=8
[0 ns] s_byte=0 u_byte=0
[0 ns] s_byte=127 u_byte=127
[0 ns] s_byte=-128 u_byte=1128
[0 ns] s_byte=-128 u_byte=255
[0 ns] s_byte=-128 u_byte=0
ncsim: *W,RNQUIE: Simulation is complete.