前置条件：
DDR模式
LR
RISE:1.9-2.1
FALL:1.9-2.1
约束情况1：
value：0
IBUF-BUFG-IDELAYE2-IDDR
value：0
IBUF-IDELAYE2-IDDR
module rgmii_dphy (
input wire sys_rst_n ,
input wire sys_ref_200mhz ,
//eth
input wire i_eth_rxc ,//eth rx clk
input wire i_eth_rx_ctl ,
input wire [3:0] i_eth_rxd ,
output wire o_eth_rx_clk ,
output wire o_eth_rx_vaild ,
output wire [7:0] o_eth_rx_data
);
//-------------------------------------------------------------------------------------------//
//BUFIO
wire rxc_bufio ;
//BUFR
wire rxc_bufg ;
//BUFR
wire rxc_bufr ;
//IBUF
wire [3:0] eth_rxd_buf ;
wire eth_rx_ctl_buf ;
wire [7:0] eth_rxd_data ;
wire eth_rxd_vaild ;//enable
wire eth_rx_error ;
reg r1_eth_rx_vaild;
reg [7:0] r1_eth_rx_data ;
//delay
wire delay_rxc ;
wire [3:0] delay_rxd ;
wire delay_rx_ctrl ;
//-------------------------------------------------------------------------------------------//
// assign o_eth_rx_clk = rxc_bufg ;
assign o_eth_rx_vaild = r1_eth_rx_vaild;
assign o_eth_rx_data = r1_eth_rx_data ;
always @(posedge i_eth_rxc or negedge sys_rst_n) begin
if(sys_rst_n == 1'b0) begin
r1_eth_rx_vaild <= 1'd0;
r1_eth_rx_data <= 8'd0;
end else if(eth_rxd_vaild == 1'b1) begin
r1_eth_rx_vaild <= eth_rxd_vaild;
r1_eth_rx_data <= eth_rxd_data ;
end else begin
r1_eth_rx_vaild <= 1'd0;
r1_eth_rx_data <= 8'd0;
end
end
//-------------------------------------------------------------------------------------------//
assign o_eth_rx_clk = i_eth_rxc ;
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst_eth_rxc (
.RDY (), // 1-bit output: Ready output
.REFCLK(sys_ref_200mhz), // 1-bit input: Reference clock input
.RST ( 1'b0 ) // 1-bit input: Active high reset input
);
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "DATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rxc (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rxc ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( i_eth_rxc ), // 1-bit input: Internal delay data input
.IDATAIN ( 1'b0 ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
//-------------------------------------------------------------------------------------------//
// BUFIO BUFIO_inst_eth_rxc (
// .O( rxc_bufio ), // 1-bit output: Clock output (connect to I/O clock loads).
// .I( i_eth_rxc ) // 1-bit input: Clock input (connect to an IBUF or BUFMR).
// );
// BUFG BUFG_inst_eth_rxc (
// .O( rxc_bufg ), // 1-bit output: Clock output
// .I( i_eth_rxc ) // 1-bit input: Clock input
// );
//-------------------------------------------------------------------------------------------//
//-------------------------------------------------------------------------------------------//
generate
genvar rxd_i;
for(rxd_i = 0;rxd_i < 4;rxd_i = rxd_i + 1)begin:iddr_block
IBUF #(
.IBUF_LOW_PWR( "TRUE" ),// Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
.IOSTANDARD ( "DEFAULT" ) // Specify the input I/O standard
) IBUF_inst (
.O( eth_rxd_buf[rxd_i] ), // Buffer output
.I( i_eth_rxd[rxd_i] ) // Buffer input (connect directly to top-level port)
);
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "DATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rxd (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rxd[rxd_i] ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( eth_rxd_buf[rxd_i] ), // 1-bit input: Internal delay data input
.IDATAIN ( 1'b0 ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst_eth_rxd (
.Q1 ( eth_rxd_data[rxd_i] ), // 1-bit output for positive edge of clock
.Q2 ( eth_rxd_data[rxd_i+4] ), // 1-bit output for negative edge of clock
.C ( delay_rxc ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( delay_rxd[rxd_i] ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
end
endgenerate
// ctrl
IBUF #(
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUF_inst_eth_ctrl (
.O( eth_rx_ctl_buf ), // Buffer output
.I( i_eth_rx_ctl ) // Buffer input (connect directly to top-level port)
);
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTR
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "DATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rx_ctrl (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rx_ctrl ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( eth_rx_ctl_buf ), // 1-bit input: Internal delay data input
.IDATAIN ( 1'b0 ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst_eth_rx_ctrl (
.Q1 ( eth_rxd_vaild ), // 1-bit output for positive edge of clock
.Q2 ( eth_rx_error ), // 1-bit output for negative edge of clock
.C ( delay_rxc ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( delay_rx_ctrl ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
//-------------------------------------------------------------------------------------------//
endmodule
View Code
约束情况2：
DATA端口去掉IBUF,IDELAY直接连接IO
module rgmii_dphy (
input wire sys_rst_n ,
input wire sys_ref_200mhz ,
//eth
input wire i_eth_rxc ,//eth rx clk
input wire i_eth_rx_ctl ,
input wire [3:0] i_eth_rxd ,
output wire o_eth_rx_clk ,
output wire o_eth_rx_vaild ,
output wire [7:0] o_eth_rx_data
);
//-------------------------------------------------------------------------------------------//
//BUFIO
wire rxc_bufio ;
//BUFR
wire rxc_bufg ;
//BUFR
wire rxc_bufr ;
//IBUF
wire [3:0] eth_rxd_buf ;
wire eth_rx_ctl_buf ;
wire [7:0] eth_rxd_data ;
wire eth_rxd_vaild ;//enable
wire eth_rx_error ;
reg r1_eth_rx_vaild;
reg [7:0] r1_eth_rx_data ;
//delay
wire delay_rxc ;
wire [3:0] delay_rxd ;
wire delay_rx_ctrl ;
//-------------------------------------------------------------------------------------------//
// assign o_eth_rx_clk = rxc_bufg ;
assign o_eth_rx_vaild = r1_eth_rx_vaild;
assign o_eth_rx_data = r1_eth_rx_data ;
always @(posedge i_eth_rxc or negedge sys_rst_n) begin
if(sys_rst_n == 1'b0) begin
r1_eth_rx_vaild <= 1'd0;
r1_eth_rx_data <= 8'd0;
end else if(eth_rxd_vaild == 1'b1) begin
r1_eth_rx_vaild <= eth_rxd_vaild;
r1_eth_rx_data <= eth_rxd_data ;
end else begin
r1_eth_rx_vaild <= 1'd0;
r1_eth_rx_data <= 8'd0;
end
end
//-------------------------------------------------------------------------------------------//
assign o_eth_rx_clk = i_eth_rxc ;
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst_eth_rxc (
.RDY (), // 1-bit output: Ready output
.REFCLK(sys_ref_200mhz), // 1-bit input: Reference clock input
.RST ( 1'b0 ) // 1-bit input: Active high reset input
);
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "DATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rxc (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rxc ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( i_eth_rxc ), // 1-bit input: Internal delay data input
.IDATAIN ( 1'b0 ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
//-------------------------------------------------------------------------------------------//
// BUFIO BUFIO_inst_eth_rxc (
// .O( rxc_bufio ), // 1-bit output: Clock output (connect to I/O clock loads).
// .I( i_eth_rxc ) // 1-bit input: Clock input (connect to an IBUF or BUFMR).
// );
// BUFG BUFG_inst_eth_rxc (
// .O( rxc_bufg ), // 1-bit output: Clock output
// .I( i_eth_rxc ) // 1-bit input: Clock input
// );
//-------------------------------------------------------------------------------------------//
//-------------------------------------------------------------------------------------------//
generate
genvar rxd_i;
for(rxd_i = 0;rxd_i < 4;rxd_i = rxd_i + 1)begin:iddr_block
// IBUF #(
// .IBUF_LOW_PWR( "TRUE" ),// Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
// .IOSTANDARD ( "DEFAULT" ) // Specify the input I/O standard
// ) IBUF_inst (
// .O( eth_rxd_buf[rxd_i] ), // Buffer output
// .I( i_eth_rxd[rxd_i] ) // Buffer input (connect directly to top-level port)
// );
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rxd (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rxd[rxd_i] ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( i_eth_rxd[rxd_i] ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst_eth_rxd (
.Q1 ( eth_rxd_data[rxd_i] ), // 1-bit output for positive edge of clock
.Q2 ( eth_rxd_data[rxd_i+4] ), // 1-bit output for negative edge of clock
.C ( delay_rxc ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( delay_rxd[rxd_i] ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
end
endgenerate
// ctrl
// IBUF #(
// .IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
// .IOSTANDARD("DEFAULT") // Specify the input I/O standard
// ) IBUF_inst_eth_ctrl (
// .O( eth_rx_ctl_buf ), // Buffer output
// .I( i_eth_rx_ctl ) // Buffer input (connect directly to top-level port)
// );
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTR
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rx_ctrl (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rx_ctrl ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( i_eth_rx_ctl ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst_eth_rx_ctrl (
.Q1 ( eth_rxd_vaild ), // 1-bit output for positive edge of clock
.Q2 ( eth_rx_error ), // 1-bit output for negative edge of clock
.C ( delay_rxc ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( delay_rx_ctrl ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
//-------------------------------------------------------------------------------------------//
endmodule
View Code
module rgmii_dphy (
input wire sys_rst_n ,
input wire sys_ref_200mhz ,
//eth
input wire i_eth_rxc ,//eth rx clk
input wire i_eth_rx_ctl ,
input wire [3:0] i_eth_rxd ,
output wire o_eth_rx_clk ,
output wire o_eth_rx_vaild ,
output wire [7:0] o_eth_rx_data
);
//-------------------------------------------------------------------------------------------//
//BUFIO
wire rxc_bufio ;
//BUFR
wire rxc_bufg ;
//BUFR
wire rxc_bufr ;
//IBUF
wire [3:0] eth_rxd_buf ;
wire eth_rx_ctl_buf ;
wire [7:0] eth_rxd_data ;
wire eth_rxd_vaild ;//enable
wire eth_rx_error ;
reg r1_eth_rx_vaild;
reg [7:0] r1_eth_rx_data ;
//delay
wire delay_rxc ;
wire [3:0] delay_rxd ;
wire delay_rx_ctrl ;
//-------------------------------------------------------------------------------------------//
// assign o_eth_rx_clk = rxc_bufg ;
assign o_eth_rx_vaild = r1_eth_rx_vaild;
assign o_eth_rx_data = r1_eth_rx_data ;
always @(posedge i_eth_rxc or negedge sys_rst_n) begin
if(sys_rst_n == 1'b0) begin
r1_eth_rx_vaild <= 1'd0;
r1_eth_rx_data <= 8'd0;
end else if(eth_rxd_vaild == 1'b1) begin
r1_eth_rx_vaild <= eth_rxd_vaild;
r1_eth_rx_data <= eth_rxd_data ;
end else begin
r1_eth_rx_vaild <= 1'd0;
r1_eth_rx_data <= 8'd0;
end
end
//-------------------------------------------------------------------------------------------//
assign o_eth_rx_clk = i_eth_rxc ;
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst_eth_rxc (
.RDY (), // 1-bit output: Ready output
.REFCLK(sys_ref_200mhz), // 1-bit input: Reference clock input
.RST ( 1'b0 ) // 1-bit input: Active high reset input
);
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "DATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rxc (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rxc ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( i_eth_rxc ), // 1-bit input: Internal delay data input
.IDATAIN ( 1'b0 ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
//-------------------------------------------------------------------------------------------//
// BUFIO BUFIO_inst_eth_rxc (
// .O( rxc_bufio ), // 1-bit output: Clock output (connect to I/O clock loads).
// .I( i_eth_rxc ) // 1-bit input: Clock input (connect to an IBUF or BUFMR).
// );
// BUFG BUFG_inst_eth_rxc (
// .O( rxc_bufg ), // 1-bit output: Clock output
// .I( i_eth_rxc ) // 1-bit input: Clock input
// );
//-------------------------------------------------------------------------------------------//
//-------------------------------------------------------------------------------------------//
generate
genvar rxd_i;
for(rxd_i = 0;rxd_i < 4;rxd_i = rxd_i + 1)begin:iddr_block
// IBUF #(
// .IBUF_LOW_PWR( "TRUE" ),// Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
// .IOSTANDARD ( "DEFAULT" ) // Specify the input I/O standard
// ) IBUF_inst (
// .O( eth_rxd_buf[rxd_i] ), // Buffer output
// .I( i_eth_rxd[rxd_i] ) // Buffer input (connect directly to top-level port)
// );
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rxd (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rxd[rxd_i] ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( i_eth_rxd[rxd_i] ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst_eth_rxd (
.Q1 ( eth_rxd_data[rxd_i] ), // 1-bit output for positive edge of clock
.Q2 ( eth_rxd_data[rxd_i+4] ), // 1-bit output for negative edge of clock
.C ( delay_rxc ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( delay_rxd[rxd_i] ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
end
endgenerate
// ctrl
// IBUF #(
// .IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
// .IOSTANDARD("DEFAULT") // Specify the input I/O standard
// ) IBUF_inst_eth_ctrl (
// .O( eth_rx_ctl_buf ), // Buffer output
// .I( i_eth_rx_ctl ) // Buffer input (connect directly to top-level port)
// );
(* IODELAY_GROUP = "RGMII_RX" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTR
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 0 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst_eth_rx_ctrl (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( delay_rx_ctrl ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( i_eth_rx_ctl ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_inst_eth_rx_ctrl (
.Q1 ( eth_rxd_vaild ), // 1-bit output for positive edge of clock
.Q2 ( eth_rx_error ), // 1-bit output for negative edge of clock
.C ( delay_rxc ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( delay_rx_ctrl ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
//-------------------------------------------------------------------------------------------//
endmodule
View Code
我想还得再考虑一下IO资源的耗用，这里加上。
显然因为时钟延迟太少产生了保持时间的违例。
标签：wire,vaild,rxc,rx,约束,测试,IDELAY,input,eth From： https://www.cnblogs.com/VerweileDoch/p/18161952