4-bit shift register

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

areset: Resets shift register to zero.
load: Loads shift register with data[3:0] instead of shifting.
ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
q: The contents of the shift register.
If both the load and ena inputs are asserted (1), the load input has higher priority.

题目网站

 1 module top_module(
 2     input clk,
 3     input areset,  // async active-high reset to zero
 4     input load,
 5     input ena,
 6     input [3:0] data,
 7     output reg [3:0] q); 
 8 always @(posedge clk or posedge areset)begin
 9     if(areset)begin   //在最高位次首先实现reset=1时的复位
10             q <= 4'b0;
11         end
12     else if(load) begin   //如果load=1，则进行加载
13             q <= data;
14         end
15     else if(ena)begin   //实现右移的功能，这个{1'b0,q[3:1]}写得巧妙
16             q <= {1'b0,q[3:1]};
17         end
18         else begin
19             q <= q;
20         end
21     end
22 
23 endmodule

再写：
上面写的代码仿真的时候没有出错，但是应该是没有完成题目中If both the load and ena inputs are asserted (1), the load input has higher priority.的要求，修改如下：

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always@(posedge clk,posedge areset)begin   
        if(areset)begin
            q<=4'b0;
        end
        else begin
            case({load,ena}) 
                2'b10:begin
                    q<=data;
                end
                2'b01:begin
                    q<={1'b0,q[3:1]};
                end
                2'b11:begin
                    q<=data;
                end
                3'b00:begin
                    q<=q;
                end
                endcase
            end
    end
endmodule