虽然大部分摄像头都不支持热拔插,但我觉得思考一下相关问题还是有意义的。
先说结论:处理断流的根本在于同步信号。
正所谓,输入端通常会有同步头、同步行之类的时间串口,通过对这个期间的信号做处理以后使用其上升沿作为标志,用来重置存储地址和FIFO是处理输入同步的有效方法。
代码:
1 //W Sync Port 2 //wrclk 3 reg r1_pre_vs ; 4 wire Pose_pre_vs ; 5 wire Nege_pre_vs ; 6 wire Ext_Pose_pre_vs ; 7 //sysclk 8 reg sys_pre_vs ; 9 reg r1_sys_pre_vs ; 10 reg sys_Pose_pre_vs ; 11 reg sys_Nege_pre_vs ; 12 reg r_sys_Nege_pre_vs; 13 reg [1:0] wr_index ; 14 reg [C_M_AXI_ADDR_WIDTH-1 : 0] wr_base_addr ; 15 16 always @(posedge I_Pre_clk) begin 17 r1_pre_vs <= I_Pre_vs; 18 end 19 20 assign Pose_pre_vs = (I_Pre_vs == 1'b1)&&(r1_pre_vs == 1'b0); 21 assign Nege_pre_vs = (I_Pre_vs == 1'b0)&&(r1_pre_vs == 1'b1); 22 23 always@(posedge M_AXI_ACLK) begin 24 sys_pre_vs <= I_Pre_vs ; 25 r1_sys_pre_vs <= sys_pre_vs; 26 r_sys_Nege_pre_vs <= sys_Nege_pre_vs; 27 end 28 29 always @(posedge M_AXI_ACLK) begin 30 if(M_AXI_ARESETN == 1'b0) begin 31 sys_Pose_pre_vs <= 1'b0; 32 sys_Nege_pre_vs <= 1'b0; 33 end else if(sys_pre_vs==1'b1&&r1_sys_pre_vs==1'b0) begin 34 sys_Pose_pre_vs <= 1'b1; 35 sys_Nege_pre_vs <= 1'b0; 36 end else if(sys_pre_vs==1'b0&&r1_sys_pre_vs==1'b1) begin 37 sys_Pose_pre_vs <= 1'b0; 38 sys_Nege_pre_vs <= 1'b1; 39 end else begin 40 sys_Pose_pre_vs <= 1'b0; 41 sys_Nege_pre_vs <= 1'b0; 42 end 43 end 44 45 46 Data_sync_ext Data_sync_ext_Inst0( 47 .clka ( I_Pre_clk ), 48 .rst_n ( M_AXI_ARESETN ), 49 .pulse_a ( Pose_pre_vs ), 50 .ext_pulse_a ( Ext_Pose_pre_vs ) 51 ); 52 53 always@(posedge M_AXI_ACLK) 54 if(M_AXI_ARESETN == 1'b0) begin 55 wr_index <= 'd1; 56 end else if(sys_Nege_pre_vs == 1'b1&&wr_index == AXI_Buff_NUM) begin 57 wr_index <= 'd1; 58 end else if(sys_Nege_pre_vs==1'b1) begin 59 wr_index <= wr_index + 1'b1; 60 end else begin 61 wr_index <= wr_index; 62 end 63 64 assign O_wr_index = wr_index; 65 66 always@(posedge M_AXI_ACLK) 67 if(M_AXI_ARESETN == 1'b0) begin 68 wr_base_addr <= 0; 69 end else if(sys_Nege_pre_vs == 1'b1&&wr_index == AXI_Buff_NUM) begin 70 wr_base_addr <= 0; 71 end else if(sys_Nege_pre_vs == 1'b1) begin 72 wr_base_addr <= wr_base_addr + Total_Frame_Offset; 73 end else begin 74 wr_base_addr <= wr_base_addr; 75 endView Code
而处理输出就比较简单了,因为是你自己定义的,自己生成或使用现有的VGA或其他接口的同步帧即可。
标签:pre,视频,wire,断流,sys,vs,思考,reg,Nege From: https://www.cnblogs.com/VerweileDoch/p/18077164