Verilog 上升沿与下降沿检测

FPGA中常用的上升沿检测和下降沿检测代码，使用的verilog hdl语言

//上升沿检测
module pose_chk(clk, in, out);
input clk, in;
output out;

reg curr, last;

always@(posedge clk)
begin
    curr <= in;
    last <= curr;
end

assign out = curr & (~last);

endmodule

//下降沿检测
module nege_chk(clk, in, out);
input clk, in;
output out;

reg curr, last;

always@(posedge clk)
begin
    curr <= in;
    last <= curr;
end

assign out = ~curr & (last);

endmodule

使用梯度下降法求无约束问题最优解