FPGA实现分频器

 1 `timescale 1ns/1ns
 2 
 3 module  fpq_tb();
 4 
 5 
 6 reg [0:0]  sys_clk;
 7 reg [0:0]  sys_rst_n;
 8 wire [0:0] clk_out;
 9 
10 initial begin
11           sys_clk=1'b0;
12           sys_rst_n=1'b0;
13           #50;
14           sys_rst_n=1;  
15           #500;
16           $stop;
17         end
18         
19         
20 always #10   sys_clk<=~sys_clk ;  
21 
22 
23  divider
24 #(
25 .DIV_PARAMETER(8'D7)
26 )
27 u_divider
28 (
29              .sys_clk    (sys_clk),
30              .sys_rst_n  (sys_rst_n),
31              .clk_out    (clk_out)
32 
33 );
34 
35 
36 
37 endmodule

 1 module  divider
 2 #(
 3 parameter[7:0] DIV_PARAMETER = 8'D2
 4 )
 5 (
 6              input  wire  [0:0] sys_clk ,
 7              input  wire  [0:0] sys_rst_n,
 8              output wire   [0:0] clk_out
 9 
10 );
11 
12 localparam [7:0] DIV_MAX_ODD =DIV_PARAMETER/2-8'd1 ;
13 localparam [7:0] DIV_EVEN =DIV_PARAMETER/2;
14 
15 reg [7:0] odd_cnt;
16 reg [7:0] even_cnt;
17 reg [0:0] clk_odd_out;
18 reg [0:0] clk_even_1;
19 reg [0:0] clk_even_2;
20 
21 
22 //对偶分频的时钟进行计数
23 always @(posedge sys_clk or negedge sys_rst_n )
24      begin
25         if(sys_rst_n==1'b0)
26             odd_cnt<=8'd0;
27         else if(odd_cnt>=DIV_MAX_ODD)
28             odd_cnt<=8'd0;
29         else 
30             odd_cnt<=odd_cnt+8'd1;       
31      end
32 //当偶分频的时钟计数到达分频系数的一半时，对偶分频时钟进行翻转
33 always @(posedge sys_clk or negedge sys_rst_n )
34      begin
35         if(sys_rst_n==1'b0)
36            clk_odd_out<=1'b0;
37         else if(odd_cnt>=DIV_MAX_ODD)
38            clk_odd_out<=~clk_odd_out;
39         else 
40             clk_odd_out<=clk_odd_out;       
41      end
42 //对奇分频的时钟进行计数到达分频系数减1时归零    
43 always @(posedge sys_clk or negedge sys_rst_n )
44      begin
45         if(sys_rst_n==1'b0)
46             even_cnt<=8'd0;
47         else if(even_cnt>=DIV_PARAMETER-8'd1)
48             even_cnt<=8'd0;
49         else 
50             even_cnt<=even_cnt+8'd1;       
51      end    
52 //在posedge sys_clk对奇分频的计数到达分频系数一半时clk_even_1拉高，当到达分频系数减1时clk_even_1拉低，其它时候不变   
53 always @(posedge sys_clk or negedge sys_rst_n )
54      begin
55         if(sys_rst_n==1'b0)
56             clk_even_1<=1'b0;
57         else if(even_cnt==DIV_EVEN)
58             clk_even_1<=1'b1;
59         else if(even_cnt>=DIV_PARAMETER-8'd1)   
60             clk_even_1<=1'b0;
61         else 
62              clk_even_1<=clk_even_1;    
63         
64      end
65 //在negedge sys_clk对奇分频的计数到达分频系数一半时clk_even_1拉高，当到达分频系数减1时clk_even_1拉低，其它时候不变      
66 always @(negedge sys_clk or negedge sys_rst_n )
67      begin
68         if(sys_rst_n==1'b0)
69             clk_even_2<=1'b0;
70         else if(even_cnt==DIV_EVEN)
71             clk_even_2<=1'b1;
72         else if(even_cnt>=DIV_PARAMETER-8'd1)   
73             clk_even_2<=1'b0;
74         else 
75              clk_even_2<=clk_even_2;    
76         
77      end   
78  
79 assign clk_out =(DIV_PARAMETER%2)? (clk_even_1|clk_even_2): clk_odd_out;    
80    
81 endmodule