模型机下载【FPGA模型机课程设计】
- 前言
- 推荐
- 单周期CPU模型机下载
- 安排
- 测试与结果
- 5.7.2模型机下载FPGA设计
- 代码设计
- MIOC
- IO
- IO1
- SoC
- InstMem
- 附录
- 0 框架
- E MIOC 接口
- F IO 外设
- IO1 测试MIOC分流
- 9 InstMem 指令存储器
- 10 SoC 顶层
- 最后
前言
2023-5-27 07:55:09
周六早上睡不着了起来学习
推荐
5模型机整体的联调【FPGA模型机课程设计】
单周期CPU模型机下载
安排
流水线CPU设计遇到困难
先实现一个模型机下载的功能设计
测试与结果
使用IO1测试
//测试FPGA
//用户空间的访问0000_0000~6FFF_FFFF
//(r1)=0000 1100
// +0000 0018
//addr=0000 1118
// =1000100011000 字节地址
// =100 0100 0110 字地址
// =446H 只有1K空间 太大电脑内存不够 实际大小有7000_0000
// =46H 丢掉了高位的1位
// =70
//datamem[70]=(r6)=00001120
instmem[6]=32'b101011_00001_00110_0000_0000_0001_1000; //sw r6,0x18(r1)
//(r7)=datamem[70]
instmem[7]=32'b100011_00001_00111_0000_0000_0001_1000; //lw r7,0x18(r1)
//IO空间的访问7000_0000~7FFF_FFFF
//lui R0,7000 --R8 --70000000
instmem [8] = 32'h3C087000;
//(r8)=70000000
// +0000 0018
//addr=7000 0018
// =0111 0000 0000 0000 0000 0000 0001 1000 字节地址
// =0111 0000 0000 0000 0001 0000 0001 10 字地址
// =1C00 0406H 只有1K空间 实际大小有1000_0000
// =06H 丢掉了多余位 1K=400H
// =6
//iomem[6]=(r6)=00001120
instmem[9]=32'b101011_01000_00110_0000_0000_0001_1000; //sw r6,0x18(r8)
//(r9)=iomem[6]
instmem[10]=32'b100011_01000_01001_0000_0000_0001_1000; //lw r9,0x18(r8)regFile、DataMem、IO数据没有问题
可以看到MIOC的波形是正确的
5.7.2模型机下载FPGA设计
参考：教学资料
对于用户空间
因为我们采用的是哈佛结构，指令存储器和数据存储器分开
所以用户空间事实上是给数据存储器用的
顶层设计
只需MIOC接受MEM的读写信号
再进行分流，对地址进行判断
如果是数据存储地址，就对DataMem进行访问
如果是IO地址，就对IO进行访问
MIOC是接口模块，不要把它放到CPU里面
放到外面，与DataMem和IO连接起来
可以看到MIOC的设计
就是组合逻辑
写逻辑
读逻辑
Soc顶层设计
IOinterface与FPGA开发板相连
举例：数码管、灯、开关、按键
IO模块
SOC模块
代码设计
MIOC
输入Mem
输出DataMem或IO
`include "define.v"
module MIOC(
input wire memCe,
input wire memWr,
input wire [31:0] memAddr,
input wire [31:0] wtData,
input wire[31:0] ramRdData,
input wire[31:0] ioRdData,
output reg[31:0] rdData,
output reg ramCe,
output reg ramWe,
output reg [31:0] ramAddr,
output reg[31:0] ramWtData,
output reg ioCe,
output reg ioWe,
output reg[31:0] ioAddr,
output reg [31:0] ioWtData
);
always@(*)
if(memCe == `RamEnable)
// if(memAddr & 32'hF000_0000 == 32'h7000_0000) //按位与结果不对
if(memAddr >= 32'h7000_0000 && memAddr<32'h8000_0000)
begin
ioCe= `RamEnable;
ioWe = memWr;
ioAddr = memAddr;
ramCe= `RamDisable;
ramWe = `RamUnWrite;
ramAddr = `Zero;
end
else
begin
ioCe = `RamDisable;
ioWe= `RamUnWrite;
ioAddr = `Zero;
ramCe= `RamEnable;
ramWe = memWr;
ramAddr = memAddr;
end
else
begin
ioCe= `RamDisable;
ioWe= `RamUnWrite;
ioAddr = `Zero;
ramCe= `RamDisable;
ramWe = `RamUnWrite;
ramAddr = `Zero;
end
always@(*)
if(memCe == `RamEnable)
if(ramCe ==`RamEnable)
begin
rdData= ramRdData;
ramWtData = wtData;
ioWtData= `Zero;
end
else
begin
rdData = ioRdData;
ramWtData= `Zero;
ioWtData=wtData;
end
else
begin
rdData= `Zero;
ramWtData= `Zero;
ioWtData= `Zero;
end
endmoduleIO
连接外设空间
`include "define.v";
module IO(
input wire ce,
input wire clk,
input wire we,
input wire[31:0]addr,
input wire[31:0]wtData,
output reg[31:0]rdData
/*IO interface*/
);
/*access IO device*/
endmoduleIO1
为了测试MIOC的分流功能
改写IO模块，使得结果可见
实际开发中，不需要
使用存储器来观察结果
`include "define.v";
module IO(
input wire ce,
input wire clk,
input wire we,
input wire[31:0]addr,
input wire[31:0]wtData,
output reg[31:0]rdData
/*IO interface*/
);
/*access IO device*/
reg [31:0] iomem [1023 : 0];
always@(*)
if(ce == `RamDisable)
rdData = `Zero;
else
rdData = iomem[addr[11 : 2]];
always@(posedge clk)
if(ce == `RamEnable && we == `RamWrite)
iomem[addr[11 : 2]] = wtData;
else ;
endmoduleSoC
使用Mem连接MIIOC
MIOC分流到DataMem或IO
module SoC(
input wire clk,
input wire rst
/*IO interface*/
);
//FPGA
wire ramCe, ramWe, ioCe, ioWe;
wire[31:0] ramWtData, ramAddr, ramRdData;
wire[31:0] ioWtData, ioAddr, ioRdData;
//修改MIPS实例
//中断-修改
MIPS mips0(
.clk(clk),
.rst(rst),
.instruction(instruction),
.instAddr(instAddr),
.romCe(romCe),
.rdData(rdData),
.wtData(wtData),
.memAddr(memAddr),
.memCe(memCe),
.memWr(memWr),
.intr(intr),//中断
.intimer(intr[0])//中断
);
//新增
MIOC mioc0(
.memCe(memCe),
.memWr(memWr),
.memAddr(memAddr),
.wtData(wtData),
.rdData(rdData),
.ramCe(ramCe),
.ramWe(ramWe),
.ramAddr(ramAddr),
.ramRdData(ramRdData),
.ramWtData(ramWtData),
.ioCe(ioCe),
.ioWe(ioWe),
.ioAddr(ioAddr),
.ioRdData(ioRdData),
.ioWtData(ioWtData)
);
/*
//新增DataMem实例化
DataMem datamem0(
.ce(memCe),
.clk(clk),
.we(memWr),
.addr(memAddr),
.wtData(wtData),
.rdData(rdData)
);
*/
//FPGA-修改datamem
//连接MIOC 不是直接连接Mem了
DataMem datamem0(
.ce(ramCe),
.clk(clk),
.we(ramWe),
.addr(ramAddr),
.rdData(ramRdData),
.wtData(ramWtData)
);
//新增
IO io0(
.ce(ioCe),
.clk(clk),
.we(ioWe),
.addr(ioAddr),
.rdData(ioRdData),
.wtData(ioWtData)
/*IO interface*/
);
endmoduleInstMem
//测试FPGA
//用户空间的访问0000_0000~6FFF_FFFF
//(r1)=0000 1100
// +0000 0018
//addr=0000 1118
// =1000100011000 字节地址
// =100 0100 0110 字地址
// =446H 只有1K空间 太大电脑内存不够 实际大小有7000_0000
// =46H 丢掉了高位的1位
// =70
//datamem[70]=(r6)=00001120
instmem[6]=32'b101011_00001_00110_0000_0000_0001_1000; //sw r6,0x18(r1)
//(r7)=datamem[70]
instmem[7]=32'b100011_00001_00111_0000_0000_0001_1000; //lw r7,0x18(r1)
//IO空间的访问7000_0000~7FFF_FFFF
//lui R0,7000 --R8 --70000000
instmem [8] = 32'h3C087000;
//(r8)=70000000
// +0000 0018
//addr=7000 0018
// =0111 0000 0000 0000 0000 0000 0001 1000 字节地址
// =0111 0000 0000 0000 0001 0000 0001 10 字地址
// =1C00 0406H 只有1K空间 实际大小有1000_0000
// =06H 丢掉了多余位 1K=400H
// =6
//iomem[6]=(r6)=00001120
instmem[9]=32'b101011_01000_00110_0000_0000_0001_1000; //sw r6,0x18(r8)
//(r9)=iomem[6]
instmem[10]=32'b100011_01000_01001_0000_0000_0001_1000; //lw r9,0x18(r8)regFile、DataMem、IO数据没有问题
可以看到MIOC的波形是正确的
附录
0 框架
顶层设计
代码框架
E MIOC 接口
输入Mem
输出DataMem或IO
`include "define.v"
module MIOC(
input wire memCe,
input wire memWr,
input wire [31:0] memAddr,
input wire [31:0] wtData,
input wire[31:0] ramRdData,
input wire[31:0] ioRdData,
output reg[31:0] rdData,
output reg ramCe,
output reg ramWe,
output reg [31:0] ramAddr,
output reg[31:0] ramWtData,
output reg ioCe,
output reg ioWe,
output reg[31:0] ioAddr,
output reg [31:0] ioWtData
);
always@(*)
if(memCe == `RamEnable)
// if(memAddr & 32'hF000_0000 == 32'h7000_0000) //按位与结果不对
if(memAddr >= 32'h7000_0000 && memAddr<32'h8000_0000)
begin
ioCe= `RamEnable;
ioWe = memWr;
ioAddr = memAddr;
ramCe= `RamDisable;
ramWe = `RamUnWrite;
ramAddr = `Zero;
end
else
begin
ioCe = `RamDisable;
ioWe= `RamUnWrite;
ioAddr = `Zero;
ramCe= `RamEnable;
ramWe = memWr;
ramAddr = memAddr;
end
else
begin
ioCe= `RamDisable;
ioWe= `RamUnWrite;
ioAddr = `Zero;
ramCe= `RamDisable;
ramWe = `RamUnWrite;
ramAddr = `Zero;
end
always@(*)
if(memCe == `RamEnable)
if(ramCe ==`RamEnable)
begin
rdData= ramRdData;
ramWtData = wtData;
ioWtData= `Zero;
end
else
begin
rdData = ioRdData;
ramWtData= `Zero;
ioWtData=wtData;
end
else
begin
rdData= `Zero;
ramWtData= `Zero;
ioWtData= `Zero;
end
endmoduleF IO 外设
`include "define.v";
module IO(
input wire ce,
input wire clk,
input wire we,
input wire[31:0]addr,
input wire[31:0]wtData,
output reg[31:0]rdData
/*IO interface*/
);
/*access IO device*/
endmoduleIO1 测试MIOC分流
`include "define.v";
module IO(
input wire ce,
input wire clk,
input wire we,
input wire[31:0]addr,
input wire[31:0]wtData,
output reg[31:0]rdData
/*IO interface*/
);
/*access IO device*/
reg [31:0] iomem [1023 : 0];
always@(*)
if(ce == `RamDisable)
rdData = `Zero;
else
rdData = iomem[addr[11 : 2]];
always@(posedge clk)
if(ce == `RamEnable && we == `RamWrite)
iomem[addr[11 : 2]] = wtData;
else ;
endmodule9 InstMem 指令存储器
`include "define.v";
//6、指令存储器
module InstMem(
input wire ce,
input wire [31:0] addr,
output reg [31:0] data
);
reg [31:0] instmem [1023 : 0];
always@(*)
if(ce == `RomDisable)
data = `Zero;
else
data = instmem[addr[11 : 2]];
initial
begin
//指令测试
//初始化数据
//ori R0,1100 -- R1 --00001100
instmem [0] = 32'h34011100;
//ori R0,0020 -- R2 --00000020
instmem [1] = 32'h34020020;
//ori R0,ff00 -- R3 --0000ff00
instmem [2] = 32'h3403ff00;
//ori R0,ffff -- R4 --0000ffff
instmem [3] = 32'h3404ffff;
//I型指令测试
/*
//andi R0,ffff --R5 --00000000
instmem [4] = 32'h3005ffff;
//xori R0,ffff --R6 --0000ffff
instmem [5] = 32'h3806ffff;
//addi R0,ffff --R7 --ffffffff
instmem [6] = 32'h2007ffff;
// //subi R0,ffff --R8 --00000001
// instmem [7] = 32'h2408ffff;
//lui R0,ffff --R9 --ffff0000
instmem [8] = 32'h3C09ffff;
*/
//R1=00001100 R2=00000020
instmem [4] = 32'b000000_00001_00010_00101_00000_100000;//add,R5,R1,R2 00001120
instmem [5] = 32'b000000_00001_00010_00110_00000_100101;//or,R6,R1,R2 00001120
//R型指令测试
/*
instmem [6] = 32'b000000_00001_00010_00111_00000_100010;//sub,R7,R1,R2 000010e0
instmem [7] = 32'b000000_00001_00010_01000_00000_100100;//and,R8,R1,R2 00000000
instmem [8] = 32'b000000_00001_00010_01001_00000_100110;//xor,R9,R1,R2 00001120
//lui R0,ffff --R10 --ffff0000
instmem [9] = 32'h3C0Affff;
//R11=fffe0000 R12=7fff8000 R13=ffff8000
// Ra=sa={25'b0,imm[10:6]}
instmem [10] = 32'b000000_00000_01010_01011_00001_000000;//sll,R11,Ra,R10
instmem [11] = 32'b000000_00000_01010_01100_00001_000010;//srl,R12,Ra,R10
instmem [12] = 32'b000000_00000_01010_01101_00001_000011;//sra,R13,Ra,R10
*/
//J- JR型指令测试
/*
//pc=jaddr=npc(4) offset(26) 00(2)
//instmem [6] = 32'h08000001; //j 1 编码000010 pc=0004
instmem [6] = 32'h0C000002; //jal 2 编码000011 pc=0008 r31=npc001c
*/
/*
//pc=jaddr=(rs)
instmem [6] = 32'h3407000C;//ori,R7,000C
//instmem [7] = 32'b000000_00111_00000_00000_00000_001000; //jr R7 编码001000 pc=0000000C
instmem [7] = 32'b000000_00111_00000_00000_00000_001001; //jalr R7 编码001001 pc=0000000C R31=00000020
*/
/*
//J+型指令测试
//pc=jaddr=npc+S14 offset(16) 00(2)
//R1=00001100 R2=00000020 R3=000000ff R4=0000ffff R5=00001120 R6=00001120
//instmem [6] = 32'b000100_00101_00110_0000_0000_0000_0000; //beq r5,r6,0 编码000100 pc=001C
//instmem [6] = 32'b000100_00101_00110_0000_0000_0000_0001; //beq r5,r6,1 编码000100 pc=0020
//instmem [6] = 32'b000101_00001_00110_1111_1111_1111_1110; //bne r5,r6,-2 编码000101 pc=0014
//instmem [6] = 32'b000001_00010_00000_0000_0000_0000_0001; //bltz r2,r0,1 编码000001 pc=0020
instmem [6] = 32'b000111_00001_00000_1111_1111_1111_1110; //bgtz r1,r0,-2 编码010011 pc=0014
//ori R7,0001 -- R7 --00000001
instmem [7] = 32'h34070001; //ori R7 1
//ori R8,0001 -- R8 --00000001
instmem [8] = 32'h34080001; //ori R8 1
*/
/*
//(r1)=0000 1100
// +0000 0018
//addr=0000 1118
// =1000100011000 字节地址
// =100 0100 0110 字地址
// =446H 只有1K空间
// =46H 丢掉了高位的1位
// =70
//mem[70]=(r6)
instmem[6]=32'b101011_00001_00110_0000_0000_0001_1000; //sw r6,0x18(r1)
//(r7)=mem[70]
instmem[7]=32'b100011_00001_00111_0000_0000_0001_1000; //lw r7,0x18(r1)
*/
//测试12条MIPS指令
/*
//测试slt
//R1=00001100 R2=00000020
instmem [6] = 32'b000000_00001_00010_00111_00000_101010;//slt,R7,R1,R2 00000000
//lui R0,ffff --R8 --ffff0000
instmem [7] = 32'h3C08ffff;
//ori R8,ffff --R8 --ffffffff
instmem [8] = 32'b001101_01000_01000_1111_1111_1111_1111;
//lui R0,ffff --R9 --ffff0000
instmem [9] = 32'h3C09ffff;
//ori R9,ffff --R9 --fffffffe
instmem [10] = 32'b001101_01001_01001_1111_1111_1111_1110;
//R8=ffffffff(-1) R9=fffffffe(-2)
instmem [11] = 32'b000000_01001_01000_01010_00000_101010;//slt,R10,R9,R8 00000001
*/
/*
//测试乘除
//R1=00001100 R2=00000020
//multu,R1,R2 0_22000
instmem [6] = 32'b000000_00001_00010_00000_00000_011001;//multu,R1,R2
//ori R7,ffff -- R7 --0000ffff
instmem [7] = 32'h3407ffff; //ori R7 ffff
//sll R7,R7,10h -- R7 --ffff0000
instmem [8] = 32'b000000_00000_00111_00111_10000_000000;//sll R7,R7,10h
//mult R7,R2 ffffffff_ffe00000
instmem [9] = 32'b000000_00111_00010_00000_00000_011000;//mult R7,R2
//divu r1,r2 88_0
instmem [10] = 32'b000000_00001_00010_00000_00000_011011;//divu r1,r2
//div r3,r2 fffff800_0
instmem [11] = 32'b000000_00111_00010_00000_00000_011010;//div r7,r2
*/
/*
//测试剩余4条指令
//R1=00001100 R2=00000020
//mthi,R1--hi=00001100
instmem [6] = 32'b000000_00001_00000_00000_00000_010001;//mthi,R1
//mtlo,R2--lo=00000020
instmem [7] = 32'b000000_00010_00000_00000_00000_010011;//mtlo,R2
//mfhi,R7--R7=00001100
instmem [8] = 32'b000000_00000_00000_00111_00000_010000;//mfhi,R7
//mflo,R8--R8=00000020
instmem [9] = 32'b000000_00000_00000_01000_00000_010010;//mflo,R8
*/
/*
//测试原子指令
//计算地址说明
//(r1)=0000 1100
// +0000 0020
//addr=0000 1120
// =1000100100000 字节地址
// =100 0100 1000 字地址
// =448H 只有1K空间
// =48H 丢掉了高位的1位
// =72
//mem[72]<-->(r7)
//测试功能
//顺利的运行
//R1=00001100 R2=00000020
//Lpt: LL r7,0x20(r1) //读取程序里的信号量，LLibt=1
//ll r7,0x20(r2) --(r7)=mem[72]=0
instmem [6] = 32'b110000_00001_00111_0000_0000_0010_0000;//ll r7,0x20(r1)
//if(r7 == clearFlag) //判断信号是否被占用，为clearFlag表示没占用
//pc=jaddr=npc+S14 offset(16) 00(2)
//bne,r7,r0,else(+4)
instmem [7] = 32'b000101_00111_00000_0000_0000_0000_0100;//bne,r7,r0,else(+4)
//{
// MOV r7, setFlag //设置本程序的占用标志
//ori R7,ffff -- R7 --0000ffff
instmem [8] = 32'h3407ffff; //ori R7 ffff
// SC r7, 0x20(r1) //设置到信号量里
instmem [9] = 32'b111000_00001_00111_0000_0000_0010_0000;//sc r7,0x20(r1)
// if(r7 == 1) goto Success//如果信号量设置成功,r1就会为1
//pc=jaddr=npc+S14 offset(16) 00(2)
//bne,r1,r0,Success(+2)
instmem [10] = 32'b000101_00111_00000_0000_0000_0000_0010;//bne,r7,r0,Success(+2)
// //如果信号量没有设置成功,重新读信号量，即重新执行LL指令
// else goto Lpt
//j Lpt(6)
//pc=jaddr=npc(4) offset(26) 00(2)
instmem [11] = 32'h08000006;//j Lpt(6) 编码000010 pc=0018
//}
//else goto Lpt
//j Lpt(6)
//pc=jaddr=npc(4) offset(26) 00(2)
instmem [12] = 32'h08000006;//j Lpt(6) 编码000010 pc=0018
//Success:
// 访问指定的存储区域
// set r7,clearFlag
//andi R7,0000 -- R7 --00000000
instmem [13] = 32'h30070000; //andi R7,0000
// lw r7,(0x20)r1
instmem[14]=32'b100011_00001_00111_0000_0000_0010_0000; //lw r7,0x20(r1)
*/
//测试中断指令
/*
//测试syscall
instmem[6]=32'h0000000c;//syscall instruction
instmem[7]=32'h3407ffff;//ori
instmem[8]=32'h3408ffff;//ori
instmem [16]=32'h340affff;//syscall except program
instmem [17]=32'h340bffff;//ori
instmem [18]=32'h42000018;//eret inatruction
*/
/*
//测试定时中断
instmem[0] =32'h34020000; //ori $2, $0,0
instmem[1]= 32'h34010014; //ori $1, $0,20
instmem[2]= 32'h40815800; //mtc0 $1,$11 set compare=20
instmem[3]=32'h3c011000; //lui $1, 0x1000
instmem[4]=32'h34210401; //ori $1, $1,0x0401
instmem[5]= 32'h40816000; //mtc0 $1,$12 set status,enable int
instmem[6]= 32'h08000006; //lpt: j lpt
//interproc first addr Ox0050
instmem[20]= 32'h34030001; //ORI $3,$0,1
instmem[21]= 32'h34040014; //ORI S4, $0,20
instmem[22]= 32'h00431020; //ADD $2,$2,$3
instmem[23]= 32'h40015800; //MFC $1,$11 read compare
instmem[24]=32'h00240820; //ADD $1,$1,$4
instmem[25]= 32'h40815800; //MTC0 s1,$11 set compare
instmem[26]= 32'h42000018; //eret
*/
//测试FPGA
//用户空间的访问0000_0000~6FFF_FFFF
//(r1)=0000 1100
// +0000 0018
//addr=0000 1118
// =1000100011000 字节地址
// =100 0100 0110 字地址
// =446H 只有1K空间 太大电脑内存不够 实际大小有7000_0000
// =46H 丢掉了高位的1位
// =70
//datamem[70]=(r6)=00001120
instmem[6]=32'b101011_00001_00110_0000_0000_0001_1000; //sw r6,0x18(r1)
//(r7)=datamem[70]
instmem[7]=32'b100011_00001_00111_0000_0000_0001_1000; //lw r7,0x18(r1)
//IO空间的访问7000_0000~7FFF_FFFF
//lui R0,7000 --R8 --70000000
instmem [8] = 32'h3C087000;
//(r8)=70000000
// +0000 0018
//addr=7000 0018
// =0111 0000 0000 0000 0000 0000 0001 1000 字节地址
// =0111 0000 0000 0000 0001 0000 0001 10 字地址
// =1C00 0406H 只有1K空间 实际大小有1000_0000
// =06H 丢掉了多余位 1K=400H
// =6
//iomem[6]=(r6)=00001120
instmem[9]=32'b101011_01000_00110_0000_0000_0001_1000; //sw r6,0x18(r8)
//(r9)=iomem[6]
instmem[10]=32'b100011_01000_01001_0000_0000_0001_1000; //lw r9,0x18(r8)
end
endmodule10 SoC 顶层
//7、系统封装
//整合MIPS DataMem InstMem
//端口信号只需clk rst，其余信号在MIPS中增加，并且新增使用内部信号连线
//FPGA下板 整合Mem MIOC DataMem IO
module SoC(
input wire clk,
input wire rst
/*IO interface*/
);
wire [31:0] instAddr;
wire [31:0] instruction;
wire romCe;
//ls
wire memCe, memWr;
wire [31:0] memAddr;
wire [31:0] rdData;
wire [31:0] wtData;
//中断
wire[5:0] intr;
wire intimer;
assign intr={5'b0,intimer};
//FPGA
wire ramCe, ramWe, ioCe, ioWe;
wire[31:0] ramWtData, ramAddr, ramRdData;
wire[31:0] ioWtData, ioAddr, ioRdData;
//修改MIPS实例
//中断-修改
MIPS mips0(
.clk(clk),
.rst(rst),
.instruction(instruction),
.instAddr(instAddr),
.romCe(romCe),
.rdData(rdData),
.wtData(wtData),
.memAddr(memAddr),
.memCe(memCe),
.memWr(memWr),
.intr(intr),//中断
.intimer(intr[0])//中断
);
//新增
MIOC mioc0(
.memCe(memCe),
.memWr(memWr),
.memAddr(memAddr),
.wtData(wtData),
.rdData(rdData),
.ramCe(ramCe),
.ramWe(ramWe),
.ramAddr(ramAddr),
.ramRdData(ramRdData),
.ramWtData(ramWtData),
.ioCe(ioCe),
.ioWe(ioWe),
.ioAddr(ioAddr),
.ioRdData(ioRdData),
.ioWtData(ioWtData)
);
InstMem instrom0(
.ce(romCe),
.addr(instAddr),
.data(instruction)
);
/*
//新增DataMem实例化
DataMem datamem0(
.ce(memCe),
.clk(clk),
.we(memWr),
.addr(memAddr),
.wtData(wtData),
.rdData(rdData)
);
*/
//FPGA-修改datamem
//连接MIOC 不是直接连接Mem了
DataMem datamem0(
.ce(ramCe),
.clk(clk),
.we(ramWe),
.addr(ramAddr),
.rdData(ramRdData),
.wtData(ramWtData)
);
//新增
IO io0(
.ce(ioCe),
.clk(clk),
.we(ioWe),
.addr(ioAddr),
.rdData(ioRdData),
.wtData(ioWtData)
/*IO interface*/
);
endmodule最后
2023-5-27 09:08:51
测试
2023-5-27 10:49:40
你对我百般注视，
并不能构成万分之一的我，
却是一览无余的你。