USB

module usb(
	//sys
	input				clk			,
	input				rst_n		,
	//input
	input				usb_flag_a	,//EP2空标志
	input				usb_flag_b	,//EP4空标志
	input				usb_flag_c	,//EP6满标志
	//output
	output	reg [1:0]	usb_addr	,
	output	reg			usb_slcs	,
	output	reg 		usb_sloe	,
	output	reg			usb_slwr	,
	output	reg 		usb_slrd	,
	inout		[15:0]	usb_fd
);
//=========================================
//================define===================
//=========================================
parameter 	IDEL	=	5'd0;
parameter	RD_REQ	= 	5'd1;
parameter	RD_DATA	=	5'd2;
parameter	RD_OVER	= 	5'd4;
parameter	WR_REQ	= 	5'd8;
parameter	WR_OVER	= 	5'd16;



    reg	[15:0]		data_reg;//inout 输出接口数据存储
reg 			access_req;//表示EP2 有数据，EP6没有满，且不忙碌
reg 			busy;//busy 表示一次传输
reg 			usb_fd_en;
reg	[4:0]		usb_state;
reg [4:0]		i;//延时操作计数


//=========================================
//================main code================
//=========================================
assign usb_fd = usb_fd_en ? data_reg : 16'bz;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		access_req <= 1'b0;
	else if(usb_flag_a & usb_flag_c && (busy == 1'b0))
		access_req <= 1'b1;
	else
		access_req <= 1'b0;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		usb_state 	<= IDEL;
		usb_addr 	<= 2'b00;
		usb_slcs	<= 1'b0;
		usb_sloe 	<= 1'b1;
		usb_slwr	<= 1'b1;
		usb_slrd	<= 1'b1;
		usb_fd_en 	<= 1'b0;
	end
	else begin
		case(usb_state)
			IDEL:begin
				usb_addr <= 2'b00;
				usb_fd_en <= 1'b0;
				i=5'd0;
				if(access_req)begin
					usb_state <= RD_REQ;
					busy <= 1'b1;
				end
				else begin
					usb_state <= IDEL;
					busy <= 1'b0;
				end
			end
			RD_REQ:begin
				if(i == 'd2)begin
					usb_slrd <= 1'b1;
					usb_sloe <= 1'b0;
					i <= i+ 1'b1;
				end
				else if(i == 'd8)begin
					usb_slrd <= 1'b0;
					usb_sloe <= 1'b0;
					usb_state <= RD_DATA;
					i <= 'd0;
				end
				else
					i <= i+1;
			end
			RD_DATA:begin
				if(i == 'd8)begin
					usb_slrd <= 1'b1;
					usb_sloe <= 1'b0;
					data_reg <= usb_fd;
					usb_state <= RD_OVER;
				end
				else
					i <= i+1;
			end
			RD_OVER:begin
				if(i == 'd4)begin
					usb_slrd <= 1'b1;
					usb_sloe <= 1'b1;
					usb_addr <= 2'b10;
					usb_state <= WR_REQ;
					i <= 'd0;
				end
				else
					i <= i+1;
			end
			WR_REQ:begin
				if(i == 'd8)begin
					usb_slwr <= 1'b1;
					usb_state <= WR_OVER;
					i <= 'd0;
				end 
				else begin
					usb_slwr <= 1'b0;
					usb_fd_en <= 1'b1;
					i <= i+1;
				end
			end
			WR_OVER:begin
				if(i == 'd4)begin
					usb_fd_en <= 1'b0;
					busy <= 1'b0;
					i <= 'd0;
					usb_state <= IDEL;
				end
				else
					i <= i+1;
			end
			default:usb_state <= IDEL;
		endcase
	end	
end
endmodule