排序电路的testbench和覆盖率应用

module sort3(clk, xrst, a, b, c, ra, rb, rc);

input   clk,xrst;
input[3:0]   a,b,c;
output[3:0]   ra,rb,rc;
reg[3:0]   ra,rb,rc;
reg[3:0]   va,vb,vc;  //temporary variables

always@(a or b or c)
begin
     {va, vb, vc} = {a, b, c};//任务调用
     sort2(va, vb);
     sort2(va, vc);
     sort2(vb, vc);
end
always@(posedge clk or negedge xrst)
begin
    if(!xrst)
     begin
          {ra, rb, rc} <= 0;
      end
    else begin
           {ra, rb, rc} <= {va, vb, vc};
         end
     end
task sort2;

inout[3:0]   x, y;
reg[3:0]   tmp;
if(x>y)
     begin
       tmp = x;
        x = y;
        y = tmp;
      end
endtask
endmodule

`timescale 1ns/1ns

module tb_sort3();

reg clk;
reg xrst;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
wire [3:0] ra,rb,rc;

parameter CYCLE=10;

sort3 sort3(.clk(clk),
       .xrst(xrst),
       .a(a),
       .b(b),
       .c(c),
       .ra(ra),
       .rb(rb),
       .rc(rc));

initial begin
 clk = 0;
 forever begin
  #(CYCLE/2);
  clk = 1;
  #(CYCLE/2);
  clk = 0;
 end
end

initial begin
 xrst = 0;
 #(5*CYCLE);
  xrst = 1;
end

integer i;
initial begin 
   a=0;b=0;c=0;
   #(3*CYCLE);
   for(i=0;i<1000;i=i+1) begin
   a={$random}%16; b={$random}%16; c={$random}%16;
   #(2*CYCLE);
   end
   $finish;
end

reg [21:0] list;
integer sum;
integer i,j;
initial begin
   list=0; sum=0; a=0; b=0; c=0; i=0; j=0;
   #(3*CYCLE);
   for(i=0;i<1000;i=i+1) begin
   a={$random}%16; b={$random}%16; c={$random}%16;
   #(2*CYCLE);
   end

    for(j=0;j<22;j=j+1) begin
    sum =sum+list[j];
    end
    $display("function cov is %d/22",sum);
  end

always@(a or b or c) begin
  if(a<5 || a==5)                list[0]=1;
  else if(a>5 && a<10)           list[1]=1;
  else if(a>10 || a==10)         list[2]=1;

  if(b<5 || b==5)                list[3]=1;
  else if(b>5 && b<10)           list[4]=1;
  else if(b>10 || b==10)         list[5]=1;

  if(c<5 || c==5)                list[6]=1;
  else if(c>5 && c<10)           list[7]=1;
  else if(c>10 || c==10)         list[8]=1;


  if(a>b && b>c)                 list[9]=1;
  else if(a==b && b>c)           list[10]=1;
  else if(a<b && a>c)            list[11]=1;
  else if(a>b && b==c)           list[12]=1;
  else if(a<b && a==c)           list[13]=1;

  if(b>c && c>a)                 list[14]=1;
  else if(b==c && c>a)           list[15]=1;
  else if(b<c && b>a)            list[16]=1;
  else if(b<c && b==a)           list[17]=1;

  if(c>a && a>b)                 list[18]=1;
  else if(c<a && c>b)            list[19]=1;
  else if(c==a && c>b)           list[20]=1;
  else if(a==b && b==c)          list[21]=1;
end

initial begin
      #(6000*CYCLE);
	$display($time,"sim end!!!");
	$finish;
end


endmodule