除法器

标签：除法器 begin end temp clk 15 reg

module division
(
    input [15:0] A,
    input [7:0] B,
    output [15:0] result,
    output [15:0] odd
);

    reg [15:0] a_reg;
    reg [7:0] b_reg;
    reg [31:0] temp_a;
    reg [31:0] temp_b;

    integer i;

    always @(*)begin
        a_reg = A;
        b_reg = B;
    end

    always @(*)begin
        temp_a = {16'h0, a_reg};
        temp_b = {b_reg, 16'h0};

        for(i = 0; i < 16; i = i + 1)begin
            temp_a = temp_a << 1;
            if(temp_a >= temp_b)
                temp_a = temp_a - temp_b + 1;
            else
                temp_a = temp_a;
        end
    end

    assign odd = temp_a[31:16];
    assign result = temp_a[15:0];

endmodule

`timescale 1ns/1ps
module tb;
    reg clk, rst_n;
    initial begin 
    clk = 1'b0; 
    #5 clk = 1'b1; 
    forever #5 clk = ~clk;
    end

    initial begin 
    $dumpfile("showmebug.vcd"); 
    $dumpvars(0, tb); 
    end

    reg [15:0] A;
    reg [7:0] B;
    wire [15:0] result;
    wire [15:0] odd;

    initial begin
        A = 10; B = 5;
        #10;
        A = 20; B = 3;
        #10;
        A = 240; B = 12;
        #10;
        A = 560; B = 13;
        #10;
        $finish;
    end
    division inst (A, B, result, odd);
endmodule

标签：除法器,begin,end,temp,clk,15,reg
From： https://www.cnblogs.com/pu1se/p/16583690.html