标签：chipyard vlsi asap7sc7p5t STDCELLS file path technology asap7 hammer

为了做soc后端，需要对Hammer进行了解，以产生正确的后端文件，并分析嵌入新工艺的可能性。

一、hammer中的工艺设置和使用

工艺相关由.tech.json和.yml格式的文件来提供。

1，JSON

指向pdk的pointer和基础的工艺约束，不能被覆盖。

1，设置工艺库位置

用户可能在服务器自己安装pdk，此时需要在tech.json中指定：

"name": "ASAP7 Library",
"grid_unit": "0.001",   //设置工艺的单位
"time_unit": "1 ps",    //单位
"installs": [  //pdk的服务器位置
  {
    "path": "$PDK",
    "base var": "technology.asap7.pdk_install_dir"
  },
  {
    "path": "$STDCELLS",
    "base var": "technology.asap7.stdcell_install_dir"
  },
  {
    "path": "tech-asap7-cache",
    "base var": ""
  }
],
"tarballs": [   //这个是tar压缩包位置，一般不需要
  {
    "path": "ASAP7_PDK_CalibreDeck.tar",
    "homepage": "http://asap.asu.edu/asap/",
    "base var": "technology.asap7.tarball_dir"
  }
],

2，LVS/DRC deck 设置

3，library 设置

用于告诉hammer标准单元和其他block的位置

"libraries": [
  {
    "lef file": "$STDCELLS/techlef_misc/asap7_tech_4x_201209.lef",
    "provides": [
      {
        "lib_type": "technology"
      }
    ]
  },
  {
    "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_TT_nldm_201020.lib.gz",
    "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
    "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
    "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
    "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
    "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
    "spice model file": {
      "path": "$PDK/models/hspice/7nm_TT.pm"
    },
    "corner": {         //what process and temperature corner that these files correspond to. 
      "nmos": "typical",
      "pmos": "typical",
      "temperature": "25 C"
    },
    "supplies": {       //what the nominal supply for these cells are. 
      "VDD": "0.70 V",
      "GND": "0 V"
    },
    "provides": [    // has several sub-keys that tell Hammer what kind of library this is (examples include stdcell, fiducials, io pad cells, bump, and level shifters) and the threshold voltage flavor of the cells
      {
        "lib_type": "stdcell",
        "vt": "RVT"
      }
    ]
  },

4，stackup

 sets up the important metal layer information for Hammer to use.  

stackups-example是一个asap7的例子

{"name": "M3", "index": 3, "direction": "vertical", "min_width": 0.072, "pitch": 0.144, "offset": 0.0, "power_strap_widths_and_spacings": [{"width_at_least": 0.0, "min_spacing": 0.072}], "power_strap_width_table": [0.072, 0.36, 0.648, 0.936, 1.224, 1.512]}

5，site

The sites field specifies the unit standard cell size of the technology for Hammer.s

6。s

 

标签：chipyard,vlsi,asap7sc7p5t,STDCELLS,file,path,technology,asap7,hammer
From： https://www.cnblogs.com/hwzhao/p/17166511.html