DE10-Nano开发板OpenOCD设置

 1 #
 2 # Altera cyclone V SoC Family
 3 #
 4 adapter driver usb_blaster
 5 usb_blaster_vid_pid  0x09fb 0x6010 0x09fb 0x6810
 6 usb_blaster_lowlevel_driver ublast2
 7 usb_blaster_firmware /home/software/altera/quartus/linux64/blaster_6810.hex
 8 
 9 if { [info exists CHIPNAME] } {
10    set _CHIPNAME $CHIPNAME
11 } else {
12    set _CHIPNAME fpgasoc
13 }
14 
15 # Subsidiary TAP: fpga
16 if { [info exists FPGA_TAPID] } {
17    set _FPGA_TAPID $FPGA_TAPID
18 } else {
19    set _FPGA_TAPID 0x02d020dd
20 }
21 jtag newtap $_CHIPNAME tap -irlen 10 -expected-id $_FPGA_TAPID
22 
23 # CoreSight Debug Access Port
24 if { [info exists DAP_TAPID] } {
25         set _DAP_TAPID $DAP_TAPID
26 } else {
27         set _DAP_TAPID 0x4ba00477
28 }
29 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
30 
31 #
32 # Cortex-A9 target
33 #
34 
35 # GDB target: Cortex-A9, using DAP, configuring only one core
36 # Base addresses of cores:
37 # core 0  -  0x80110000
38 # core 1  -  0x80112000
39 
40 set _TARGETNAME1 $_CHIPNAME.cpu.0
41 set _TARGETNAME2 $_CHIPNAME.cpu.1
42 
43 # A9 core 0
44 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
45 target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80110000
46 
47 $_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
48 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
49 
50 # A9 core 1
51 #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x80112000
52 
53 #$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
54 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
55 
56 proc cycv_dbginit {target} {
57         # General Cortex-A8/A9 debug initialisation
58         cortex_a dbginit
59 }