Verilog语法
1 Register
组合逻辑-->寄存器-->组合逻辑-->寄存器
Register是一个变量,用于存储值,并不代表一个真正的硬件DFF。
reg A,C;
// assignments are always done inside a procedure
A = 1;
C = A; //C gets the logical value 1
A = 0; //C is still 1
C = 0; //C is now 0
2 Vectors--矢量
- Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
- Left number is MS bit--左侧的数值是最高位
- Slice management
/*
busA位宽为4,表示4根线0,1,2,3
busA[2:1] 表示选择其中的第2和第3根,分别为1,2
busC=busA[2,1] 相当于 [1:0]连接到[1,2] 1与0相连,2与1相连
*/
busC = busA[2:1]
- Vector assignment (by position!)
busB = busA
/*
1 最高位 3
2 2
3 1
4 最低位 0
最高位连最高位
最低位连最低位
*/
3 Integer & Real Data Types
integer i,k;
real r;
- Use as a register(in procedure)
i = 1; // assignments occur inside procedure
r = 2.9;
k = r; // k is rounded to 3
- Integers are not initialized!--Integer是没有初始值的
- Reals are initialized to 0,0!--Real初始值为0,0
4 Time Date Type
- Special data type for simulation time measuring
- Declaration
time my_time;
- use inside procedure
//使用一个内置的系统函数
my_time=$time // get current sim time 返回当前仿真的时间
- Simulation runs at simulation time,not real time
5 Arrays
- Syntax
//类型 数组名[start:end]
integer count[1:5];// 5 integers
reg var[-15:16]; // 32 1-bit regs
reg [7:0] mem[0:1023]; //1024 8-bit regs
- Accessing array elements
- Entire element:
//mem[index] 索引
mem[10]= 8‘b10101010
- Element subfield(needs temp storage)
reg [7:0] temp;
..
temp = mem[10];
var[6 = temp[2];
标签:03,temp,--,语法,mem,Verilog,time,busA,reg
From: https://www.cnblogs.com/Icer-newer/p/17045278.html