牛客进阶刷题10：整数倍数据位宽转换8to16

比非整数倍简单

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
reg[7:0] data_lock ;
reg		 cyc_cnt	;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		cyc_cnt <= 1'b0 ;
	else if(valid_in)
		cyc_cnt <= cyc_cnt + 1 ;
	else
		cyc_cnt <= cyc_cnt ;
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		data_lock <= 'd0 ;
	else if(valid_in)
		data_lock <= data_in ;
	else
		data_lock <= data_lock ;
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		data_out <= 'd0 ;
	else if(cyc_cnt & valid_in)
		data_out <= {data_lock,data_in} ;
	else 
		data_out <= data_out	;
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		valid_out <= 1'b0 ;
	else if(cyc_cnt & valid_in)
		valid_out <= 1'b1 ;
	else
		valid_out <= 1'b0 ;
end


endmodule