使用

python3 verilog_to_tb.py test.v
需要注意的是，例化时并没有去掉最后的逗号，手动去除下。

verilog_to_tb.py

import sys
import re
def read_file(file):
    with open(file,'r') as f:
        lines = f.readlines()
    return lines
def main():
    lines = read_file('test.v')
    for line in lines:
        if(re.search(r'input\s+(\[\d+:0\])?\s*(\w*),?',line)):
            print(re.sub(r'input\s+(\[\d+:0\])?\s*(\w*),?',r'reg  \1  \2;',line),end='')
    for line in lines:
        if(re.search(r'output\s+(?:reg\s+)?(\[\d+:0\])?\s*(\w*),?',line)):
            print(re.sub(r'output\s+(?:reg\s+)?(\[\d+:0\])?\s*(\w*),?',r'wire  \1  \2;',line),end='')
    print('initial')
    print('begin')
    for line in lines:
        if(re.search(r'input\s+(\[\d+:0\])?\s*(\w*),?',line)):
            print(re.sub(r'input\s+(\[(\d+):0\])?\s*(\w*),?',r"assign \3 = \2'b0;",line),end='')
    print('end')
    for line in lines:
        if(re.search(r'module\s+(\w*)\(',line)):
            print(re.sub(r'module\s+(\w*)\(',r'\1 u_\1 (',line),end='')
            break
    print("  //input ports")
    for line in lines:
        if(re.search(r'input\s+(\[\d+:0\])?\s*(\w*),?',line)):
            print(re.sub(r'input\s+(\[\d+:0\])?\s*(\w*),?',r'  .\2(\2),',line),end='')
    print("  //output ports")
    for line in lines:
       if(re.search(r'output\s+(?:reg\s+)?(\[\d+:0\])?\s*(\w*),?',line)):
           print(re.sub(r'output\s+(?:reg\s+)?(\[\d+:0\])?\s*(\w*),?',r'  .\2(\2),',line),end='')
    print(');')
if __name__=="__main__":
    main()